[CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand
Currently, instructions doing memory accesses through a base operand that is
not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`.
This means that functions such as `TII::shouldClusterMemOps` will bail
out on instructions using an FI as a base instead of a register.
The goal of this patch is to refactor all this to return a base
operand instead of a base register.
Then in a separate patch, I will add FI support to the mem op clustering
in the MachineScheduler.
Differential Revision: https://reviews.llvm.org/D54846
llvm-svn: 347746
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index a3c160d..ff3865b 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2894,14 +2894,15 @@
}
/// Get the base register and byte offset of a load/store instr.
-bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt,
- unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI)
- const {
+bool HexagonInstrInfo::getMemOperandWithOffset(
+ MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset,
+ const TargetRegisterInfo *TRI) const {
unsigned AccessSize = 0;
- int OffsetVal = 0;
- BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
- Offset = OffsetVal;
- return BaseReg != 0;
+ BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
+ assert(!BaseOp || BaseOp->isReg() &&
+ "getMemOperandWithOffset only supports base "
+ "operands of type register.");
+ return BaseOp != nullptr;
}
/// Can these instructions execute at the same time in a bundle.
@@ -3108,21 +3109,22 @@
// Returns the base register in a memory access (load/store). The offset is
// returned in Offset and the access size is returned in AccessSize.
-// If the base register has a subregister or the offset field does not contain
-// an immediate value, return 0.
-unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
- int &Offset, unsigned &AccessSize) const {
+// If the base operand has a subregister or the offset field does not contain
+// an immediate value, return nullptr.
+MachineOperand *HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
+ int64_t &Offset,
+ unsigned &AccessSize) const {
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
getAddrMode(MI) != HexagonII::BaseLongOffset &&
!isMemOp(MI) && !isPostIncrement(MI))
- return 0;
+ return nullptr;
AccessSize = getMemAccessSize(MI);
unsigned BasePos = 0, OffsetPos = 0;
if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
- return 0;
+ return nullptr;
// Post increment updates its EA after the mem access,
// so we need to treat its offset as zero.
@@ -3131,14 +3133,14 @@
} else {
const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
if (!OffsetOp.isImm())
- return 0;
+ return nullptr;
Offset = OffsetOp.getImm();
}
const MachineOperand &BaseOp = MI.getOperand(BasePos);
if (BaseOp.getSubReg() != 0)
- return 0;
- return BaseOp.getReg();
+ return nullptr;
+ return &const_cast<MachineOperand&>(BaseOp);
}
/// Return the position of the base and offset operands for this instruction.