commit d7ffbc5c7e5d033ee3812fde2c13f1bb80044e70
author Simon Pilgrim <llvm-dev@redking.me.uk> Fri May 04 17:47:46 2018 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Fri May 04 17:47:46 2018 +0000
tree 54e65f35c8569339cc6015c72f360154121197f4
parent ded8ee07e991a25a27be9968340b109d8a6ff83f

[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.

llvm-svn: 331543

llvm/lib/Target/X86/X86Schedule.td

diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index b2f0cb0..e44aeaf 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -156,9 +156,11 @@
 defm WriteVecShift  : X86SchedWritePair; // Vector integer shifts (default).
 defm WriteVecShiftX : X86SchedWritePair; // Vector integer shifts (XMM).
 defm WriteVecShiftY : X86SchedWritePair; // Vector integer shifts (YMM/ZMM).
+defm WriteVecShiftImm : X86SchedWritePair; // Vector integer immediate shifts (default).
 defm WriteVecShiftImmX: X86SchedWritePair; // Vector integer immediate shifts (XMM).
 defm WriteVecShiftImmY: X86SchedWritePair; // Vector integer immediate shifts (YMM/ZMM).
-defm WriteVecIMul  : X86SchedWritePair; // Vector integer multiply.
+defm WriteVecIMul  : X86SchedWritePair; // Vector integer multiply (default).
+defm WriteVecIMulX : X86SchedWritePair; // Vector integer multiply (XMM).
 defm WriteVecIMulY : X86SchedWritePair; // Vector integer multiply (YMM/ZMM).
 defm WritePMULLD   : X86SchedWritePair; // Vector PMULLD.
 defm WritePMULLDY   : X86SchedWritePair; // Vector PMULLD (YMM/ZMM).
@@ -289,13 +291,13 @@
  : X86SchedWriteWidths<WriteVecShift, WriteVecShiftX,
                        WriteVecShiftY, WriteVecShiftY>;
 def SchedWriteVecShiftImm
- : X86SchedWriteWidths<WriteVecShift, WriteVecShiftImmX,
+ : X86SchedWriteWidths<WriteVecShiftImm, WriteVecShiftImmX,
                        WriteVecShiftImmY, WriteVecShiftImmY>;
 def SchedWriteVarVecShift
  : X86SchedWriteWidths<WriteVarVecShift, WriteVarVecShift,
                        WriteVarVecShiftY, WriteVarVecShiftY>;
 def SchedWriteVecIMul
- : X86SchedWriteWidths<WriteVecIMul, WriteVecIMul,
+ : X86SchedWriteWidths<WriteVecIMul, WriteVecIMulX,
                        WriteVecIMulY, WriteVecIMulY>;
 def SchedWritePMULLD
  : X86SchedWriteWidths<WritePMULLD, WritePMULLD,