Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
diff --git a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 9d2f4d0..8f1f9a6 100644
--- a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -50,7 +50,7 @@
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
- unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
+ uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
MachineRelocation GetRelocation(const MachineOperand &MO,