commit d913448b38bab6ace92ae5057b917eb57035f83b
author Eric Christopher <echristo@gmail.com> Mon Aug 04 21:25:23 2014 +0000
committer Eric Christopher <echristo@gmail.com> Mon Aug 04 21:25:23 2014 +0000
tree f2050928fa5994c44fab60d66e7d89e7cc7d7a4f
parent acc8ef273b1c3796b0fc7f19aa347115b4bc2ea4

Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

llvm-svn: 214781

llvm/lib/CodeGen/MachineInstr.cpp

diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index c9fe234..06af6f8 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -39,6 +39,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
@@ -265,7 +266,8 @@
       if (const MachineBasicBlock *MBB = MI->getParent())
         if (const MachineFunction *MF = MBB->getParent())
           TM = &MF->getTarget();
-  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr;
+  const TargetRegisterInfo *TRI =
+      TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
 
   switch (getType()) {
   case MachineOperand::MO_Register:
@@ -1517,8 +1519,8 @@
     OS << " = ";
 
   // Print the opcode name.
-  if (TM && TM->getInstrInfo())
-    OS << TM->getInstrInfo()->getName(getOpcode());
+  if (TM && TM->getSubtargetImpl()->getInstrInfo())
+    OS << TM->getSubtargetImpl()->getInstrInfo()->getName(getOpcode());
   else
     OS << "UNKNOWN";
 
@@ -1573,7 +1575,8 @@
         const MachineRegisterInfo &MRI = MF->getRegInfo();
         if (MRI.use_empty(Reg)) {
           bool HasAliasLive = false;
-          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
+          for (MCRegAliasIterator AI(
+                   Reg, TM->getSubtargetImpl()->getRegisterInfo(), true);
                AI.isValid(); ++AI) {
             unsigned AliasReg = *AI;
             if (!MRI.use_empty(AliasReg)) {
@@ -1606,7 +1609,8 @@
       else
         MO.print(OS, TM);
     } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
-      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
+      OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName(
+          MO.getImm());
     } else if (i == AsmDescOp && MO.isImm()) {
       // Pretty print the inline asm operand descriptor.
       OS << '$' << AsmOpCount++;
@@ -1624,7 +1628,11 @@
       unsigned RCID = 0;
       if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
         if (TM)
-          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
+          OS << ':'
+             << TM->getSubtargetImpl()
+                    ->getRegisterInfo()
+                    ->getRegClass(RCID)
+                    ->getName();
         else
           OS << ":RC" << RCID;
       }