commit da5b9bfa95f5c415837772e11bdd33a9c20f37cd
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 01 03:29:01 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 01 03:29:01 2019 +0000
tree 507f727d1ee6eb82ee6d40df598c8726db4d06d9
parent e6ce48422cc534488b06525634bb18b882c69506

AMDGPU/GlobalISel: Allow selection of DS atomicrmw

llvm-svn: 367507

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 9c8b951..7dc537c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1263,8 +1263,8 @@
   }
 }
 
-bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I,
-                                             CodeGenCoverage &CoverageInfo) const {
+bool AMDGPUInstructionSelector::selectG_LOAD_ATOMICRMW(MachineInstr &I,
+                                                       CodeGenCoverage &CoverageInfo) const {
   initM0(I);
   return selectImpl(I, CoverageInfo);
 }
@@ -1384,8 +1384,18 @@
       return true;
     return selectImpl(I, CoverageInfo);
   case TargetOpcode::G_LOAD:
-    return selectG_LOAD(I, CoverageInfo);
-
+  case TargetOpcode::G_ATOMIC_CMPXCHG:
+  case TargetOpcode::G_ATOMICRMW_XCHG:
+  case TargetOpcode::G_ATOMICRMW_ADD:
+  case TargetOpcode::G_ATOMICRMW_SUB:
+  case TargetOpcode::G_ATOMICRMW_AND:
+  case TargetOpcode::G_ATOMICRMW_OR:
+  case TargetOpcode::G_ATOMICRMW_XOR:
+  case TargetOpcode::G_ATOMICRMW_MIN:
+  case TargetOpcode::G_ATOMICRMW_MAX:
+  case TargetOpcode::G_ATOMICRMW_UMIN:
+  case TargetOpcode::G_ATOMICRMW_UMAX:
+    return selectG_LOAD_ATOMICRMW(I, CoverageInfo);
   case TargetOpcode::G_SELECT:
     return selectG_SELECT(I);
   case TargetOpcode::G_STORE: