commit dbd3d294e6dec8928f56975b19b91c8772d7f937
author Evan Cheng <evan.cheng@apple.com> Mon Nov 13 23:36:35 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Nov 13 23:36:35 2006 +0000
tree 61b8f3847f6b516ef35c93c05a3e7b389c4b1cbf
parent 77af6ac5e869e05ce3d49e22ea1b022ee9c6564b

Matches MachineInstr changes.

llvm-svn: 31712

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 7a342b9..96514d9 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -19,7 +19,8 @@
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
-  : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
+  : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])),
+    RI(*this) { }
 
 
 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,

llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index cc6c108..6be5e07 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -51,8 +51,9 @@
   return l - h * IMM_MULT;
 }
 
-AlphaRegisterInfo::AlphaRegisterInfo()
-  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
+AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
+  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+    TII(tii)
 {
 }
 
@@ -114,13 +115,13 @@
 	 unsigned InReg = MI->getOperand(1).getReg();
 	 Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
 	   ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-	 return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+	 return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
 	   .addReg(Alpha::F31);
        } else {           // load -> move
 	 unsigned OutReg = MI->getOperand(0).getReg();
 	 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : 
 	   ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
-	 return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
+	 return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
 	   .addReg(Alpha::F31);
        }
      }
@@ -205,11 +206,11 @@
 
       MachineInstr *New;
       if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
-         New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+        New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
           .addImm(-Amount).addReg(Alpha::R30);
       } else {
          assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
-         New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+         New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
           .addImm(Amount).addReg(Alpha::R30);
       }
 
@@ -266,7 +267,7 @@
     MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
     MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
     //insert the new
-    MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
+    MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28)
       .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
     MBB.insert(II, nMI);
   } else {

llvm/lib/Target/Alpha/AlphaRegisterInfo.h

diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
index cd10d9d..687b608 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -22,7 +22,9 @@
 class Type;
 
 struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
-  AlphaRegisterInfo();
+  const TargetInstrInfo &TII;
+
+  AlphaRegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,