Enable PostRA scheduling for SPU.
This speeds up selected test cases with up to
5% - no slowdowns observed.
llvm-svn: 120286
diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
index 0f18b7f..07c8352 100644
--- a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -14,6 +14,8 @@
#include "SPUSubtarget.h"
#include "SPU.h"
#include "SPUGenSubtarget.inc"
+#include "llvm/ADT/SmallVector.h"
+#include "SPURegisterInfo.h"
using namespace llvm;
@@ -34,3 +36,22 @@
/// producing code for the JIT.
void SPUSubtarget::SetJITMode() {
}
+
+/// Enable PostRA scheduling for optimization levels -O2 and -O3.
+bool SPUSubtarget::enablePostRAScheduler(
+ CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const {
+ Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ // CriticalPathsRCs seems to be the set of
+ // RegisterClasses that antidep breakings are performed for.
+ // Do it for all register classes
+ CriticalPathRCs.clear();
+ CriticalPathRCs.push_back(&SPU::R8CRegClass);
+ CriticalPathRCs.push_back(&SPU::R16CRegClass);
+ CriticalPathRCs.push_back(&SPU::R32CRegClass);
+ CriticalPathRCs.push_back(&SPU::R32FPRegClass);
+ CriticalPathRCs.push_back(&SPU::R64CRegClass);
+ CriticalPathRCs.push_back(&SPU::VECREGRegClass);
+ return OptLevel >= CodeGenOpt::Default;
+}
diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.h b/llvm/lib/Target/CellSPU/SPUSubtarget.h
index 147163d..d7929302 100644
--- a/llvm/lib/Target/CellSPU/SPUSubtarget.h
+++ b/llvm/lib/Target/CellSPU/SPUSubtarget.h
@@ -84,6 +84,10 @@
"-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128"
"-s:128:128-n32:64";
}
+
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const;
};
} // End llvm namespace
diff --git a/llvm/test/CodeGen/CellSPU/sext128.ll b/llvm/test/CodeGen/CellSPU/sext128.ll
index 8a5b609..027c1c5 100644
--- a/llvm/test/CodeGen/CellSPU/sext128.ll
+++ b/llvm/test/CodeGen/CellSPU/sext128.ll
@@ -13,8 +13,8 @@
; CHECK: long 66051
; CHECK: long 67438087
; CHECK-NOT: rotqmbyi
-; CHECK: rotmai
; CHECK: lqa
+; CHECK: rotmai
; CHECK: shufb
}
@@ -27,8 +27,8 @@
; CHECK: long 269488144
; CHECK: long 66051
; CHECK-NOT: rotqmbyi
-; CHECK: rotmai
; CHECK: lqa
+; CHECK: rotmai
; CHECK: shufb
}
@@ -42,8 +42,8 @@
; CHECK: long 269488144
; CHECK: long 66051
; CHECK-NOT: rotqmbyi
-; CHECK: rotmai
; CHECK: lqa
+; CHECK: rotmai
; CHECK: shufb
}
diff --git a/llvm/test/CodeGen/CellSPU/shuffles.ll b/llvm/test/CodeGen/CellSPU/shuffles.ll
index 94b5fbd..c88a258 100644
--- a/llvm/test/CodeGen/CellSPU/shuffles.ll
+++ b/llvm/test/CodeGen/CellSPU/shuffles.ll
@@ -1,4 +1,4 @@
-; RUN: llc --march=cellspu < %s | FileCheck %s
+; RUN: llc -O1 --march=cellspu < %s | FileCheck %s
define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
; CHECK: cwd {{\$.}}, 0($sp)