commit dc636c4080bfe77b1377ba7fe8b3b98c87676d87
author Evan Cheng <evan.cheng@apple.com> Mon Feb 02 09:15:04 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Feb 02 09:15:04 2009 +0000
tree 9408291fb5a935a7fe49236d8199efcab9391ea8
parent 7e4cb0a1cf0f2add6de6748825d9267a97feae5b

ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero.

llvm-svn: 63509

llvm/lib/Target/X86/X86ISelLowering.cpp

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 846acd02..7a4d34d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7515,6 +7515,14 @@
   KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
   switch (Opc) {
   default: break;
+  case X86ISD::ADD:
+  case X86ISD::SUB:
+  case X86ISD::SMUL:
+  case X86ISD::UMUL:
+    // These nodes' second result is a boolean.
+    if (Op.getResNo() == 0)
+      break;
+    // Fallthrough
   case X86ISD::SETCC:
     KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
                                        Mask.getBitWidth() - 1);