[SelectionDAG] Provide adequate register class for RegisterSDNode
When adding operands to machine instructions in case of
RegisterSDNodes, generate a COPY node in case the register class
does not match the one in the instruction definition.
Differental Revision: https://reviews.llvm.org/D35561
llvm-svn: 324733
diff --git a/llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
index 9eee9a6..a7adc2a 100644
--- a/llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | \
+; RUN: FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}tgid_x:
; EG: MEM_RAT_CACHELESS STORE_RAW T1.X
@@ -10,7 +11,8 @@
}
; FUNC-LABEL: {{^}}tgid_y:
-; EG: MEM_RAT_CACHELESS STORE_RAW T1.Y
+; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
+; EG: MOV [[REG]].X, T1.Y
define amdgpu_kernel void @tgid_y(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tgid.y() #0
@@ -19,7 +21,8 @@
}
; FUNC-LABEL: {{^}}tgid_z:
-; EG: MEM_RAT_CACHELESS STORE_RAW T1.Z
+; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
+; EG: MOV [[REG]].X, T1.Z
define amdgpu_kernel void @tgid_z(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tgid.z() #0
@@ -37,7 +40,8 @@
}
; FUNC-LABEL: {{^}}tidig_y:
-; EG: MEM_RAT_CACHELESS STORE_RAW T0.Y
+; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
+; EG: MOV [[REG]].X, T0.Y
define amdgpu_kernel void @tidig_y(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tidig.y() #0
@@ -46,7 +50,8 @@
}
; FUNC-LABEL: {{^}}tidig_z:
-; EG: MEM_RAT_CACHELESS STORE_RAW T0.Z
+; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
+; EG: MOV [[REG]].X, T0.Z
define amdgpu_kernel void @tidig_z(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tidig.z() #0