[IRTranslator] Translate unconditional branches.
llvm-svn: 263265
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index fb2f559..6fd179f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -82,11 +82,30 @@
return CLI->LowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
}
+bool IRTranslator::translateBr(const Instruction &Inst) {
+ assert(isa<BranchInst>(Inst) && "Branch expected");
+ const BranchInst &BrInst = *cast<BranchInst>(&Inst);
+ if (BrInst.isUnconditional()) {
+ const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0));
+ MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
+ MIRBuilder.buildInstr(TargetOpcode::G_BR, BrTgt.getType(), TgtBB);
+ } else {
+ assert(0 && "Not yet implemented");
+ }
+ // Link successors.
+ MachineBasicBlock &CurBB = MIRBuilder.getMBB();
+ for (const BasicBlock *Succ : BrInst.successors())
+ CurBB.addSuccessor(&getOrCreateBB(*Succ));
+ return true;
+}
+
bool IRTranslator::translate(const Instruction &Inst) {
MIRBuilder.setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
case Instruction::Add:
return translateADD(Inst);
+ case Instruction::Br:
+ return translateBr(Inst);
case Instruction::Ret:
return translateReturn(Inst);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 2a828d7..2f19bcf 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -95,3 +95,10 @@
MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) {
return buildInstr(Opcode, nullptr);
}
+
+MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty,
+ MachineBasicBlock &BB) {
+ MachineInstr *NewMI = buildInstr(Opcode, Ty);
+ MachineInstrBuilder(getMF(), NewMI).addMBB(&BB);
+ return NewMI;
+}