Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
llvm-svn: 156609
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 3af0d3f..c8966fb 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -827,6 +827,8 @@
let Inst{7-4} = 0b0111;
let Inst{9-8} = 0b00;
let Inst{27-20} = opcod;
+
+ let Unpredictable{9-8} = 0b11;
}
// Misc Arithmetic instructions.