commit ddcb95664e4d94ca9b236066e29d3d92650097aa
author Mandeep Singh Grang <mgrang@codeaurora.org> Wed May 23 22:44:08 2018 +0000
committer Mandeep Singh Grang <mgrang@codeaurora.org> Wed May 23 22:44:08 2018 +0000
tree fc2f4940c01737854dd61c9c679accddbda1c6c4
parent 767d92e3fb538690a7524c314c825df827048829

[RISCV] Lower the tail pseudoinstruction

This patch lowers the tail pseudoinstruction. This has been modeled after ARM's
tail call opt.

llvm-svn: 333137

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 8565252..e62308e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -437,6 +437,7 @@
   case TargetOpcode::DBG_VALUE:
     return 0;
   case RISCV::PseudoCALL:
+  case RISCV::PseudoTAIL:
     return 8;
   case TargetOpcode::INLINEASM: {
     const MachineFunction &MF = *MI.getParent()->getParent();