commit df3e34d9444ee5fa8c1870fd17f65970f2327784
author Hal Finkel <hfinkel@anl.gov> Wed Mar 26 22:58:37 2014 +0000
committer Hal Finkel <hfinkel@anl.gov> Wed Mar 26 22:58:37 2014 +0000
tree 947ea8952f8090684eb7ef396cfb5c5e56daffe6
parent 55e3cec6cacbd119e6da95772abbe231bc1cf9fe

[PowerPC] Generate VSX permutations for v2[fi]64 vectors

llvm-svn: 204873

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8763924..6f64018 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -570,6 +570,8 @@
       setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
       setOperationAction(ISD::STORE, MVT::v2f64, Legal);
 
+      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
+
       addRegisterClass(MVT::f64, &PPC::VSRCRegClass);
 
       addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
@@ -584,6 +586,8 @@
       setOperationAction(ISD::STORE, MVT::v2i64, Promote);
       AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
 
+      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
+
       setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
       setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
       setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
@@ -872,8 +876,8 @@
 ///
 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
                      unsigned LHSStart, unsigned RHSStart) {
-  assert(N->getValueType(0) == MVT::v16i8 &&
-         "PPC only supports shuffles by bytes!");
+  if (N->getValueType(0) != MVT::v16i8)
+    return false;
   assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
          "Unsupported merge size!");
 
@@ -910,8 +914,8 @@
 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
 /// amount, otherwise return -1.
 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
-  assert(N->getValueType(0) == MVT::v16i8 &&
-         "PPC only supports shuffles by bytes!");
+  if (N->getValueType(0) != MVT::v16i8)
+    return false;
 
   ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);