commit dfbf91e59d20b27bf7aaa411f92d07369722c009
author Andrew Lenharth <andrewl@lenharth.org> Tue Oct 31 23:46:56 2006 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue Oct 31 23:46:56 2006 +0000
tree 97d2fddfd70948adc0326e225c5094c7bb090596
parent fe43befedac43670e508682d1d9f73691600e4c4

more shotenning

llvm-svn: 31331

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 90ef7bb..7a342b9 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,7 @@
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == Alpha::BIS    || 
+  if (oc == Alpha::BISr   || 
       oc == Alpha::CPYSS  || 
       oc == Alpha::CPYST  ||
       oc == Alpha::CPYSSt || 
@@ -229,7 +229,7 @@
 
 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, 
                                 MachineBasicBlock::iterator MI) const {
-  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
     .addReg(Alpha::R31);
 }