diff --git a/llvm/lib/Target/Alpha/AlphaLLRP.cpp b/llvm/lib/Target/Alpha/AlphaLLRP.cpp
index adae36f..eb23877 100644
--- a/llvm/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/llvm/lib/Target/Alpha/AlphaLLRP.cpp
@@ -70,7 +70,7 @@
 		  prev[0] = prev[1];
 		  prev[1] = prev[2];
 		  prev[2] = 0;
-		  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31); 
 		  Changed = true; nopintro += 1;
 		  count += 1;
@@ -81,9 +81,9 @@
 			   MI->getOperand(1).getImmedValue()) {
 		  prev[0] = prev[2];
 		  prev[1] = prev[2] = 0;
-		  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31); 
-		  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31);
 		  Changed = true; nopintro += 2;
 		  count += 2;
@@ -93,11 +93,11 @@
                            && prev[2]->getOperand(1).getImmedValue() == 
                            MI->getOperand(1).getImmedValue()) {
                   prev[0] = prev[1] = prev[2] = 0;
-                  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
                   Changed = true; nopintro += 3;
                   count += 3;
@@ -130,7 +130,7 @@
           if (ub || AlignAll) {
             //we can align stuff for free at this point
             while (count % 4) {
-              BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
+              BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
                 .addReg(Alpha::R31).addReg(Alpha::R31);
               ++count;
               ++nopalign;