commit e172d7008d0c12eaa9ee2aee16ee4e13c176553c
author Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> Tue Feb 26 16:55:10 2019 +0000
committer Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> Tue Feb 26 16:55:10 2019 +0000
tree 8beb77f4f6a28e4e3c230c29202395f175c7a3ac
parent c110b5b69f19700939a56d08218dfb0abb577af9

[X86] AMD znver2 enablement

This patch enables the following

1) AMD family 17h "znver2" tune flag (-march, -mcpu).
2) ISAs that are enabled for "znver2" architecture.
3) For the time being, it uses the znver1 scheduler model.
4) Tests are updated.
5) Scheduler descriptions are yet to be put in place.

Reviewers: craig.topper

Differential Revision: https://reviews.llvm.org/D58343

llvm-svn: 354897

llvm/lib/Support/Host.cpp

diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index 35bc972..52e7080 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -916,7 +916,14 @@
     break; // "btver2"
   case 23:
     *Type = X86::AMDFAM17H;
-    *Subtype = X86::AMDFAM17H_ZNVER1;
+    if (Model >= 0x30 && Model <= 0x3f) {
+      *Subtype = X86::AMDFAM17H_ZNVER2;
+      break; // "znver2"; 30h-3fh: Zen2
+    }
+    if (Model <= 0x0f) {
+      *Subtype = X86::AMDFAM17H_ZNVER1;
+      break; // "znver1"; 00h-0Fh: Zen1
+    }
     break;
   default:
     break; // "generic"