[Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
diff --git a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
index 9df178f..badab168 100644
--- a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
+++ b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
@@ -187,7 +187,7 @@
}
attributes #0 = { nounwind readnone }
-attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #2 = { nounwind }
!llvm.module.flags = !{!0}
diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
index 87d535f..30d18b7 100644
--- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
@@ -30,4 +30,4 @@
ret i32 %v10
}
-attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" }
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
index 2d1c71c..edac4cb 100644
--- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
@@ -32,4 +32,4 @@
; Function Attrs: nounwind
declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
index 4ae2e4e..52ae69a 100644
--- a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
@@ -14,4 +14,4 @@
ret i32 %and2
}
-attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx" }
diff --git a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
index 47c49c23..713e398 100644
--- a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
@@ -53,5 +53,5 @@
declare i32 @llvm.hexagon.A2.satub(i32) #1
declare i32 @llvm.hexagon.A2.satuh(i32) #1
-attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
index 183435a..4086ca3 100644
--- a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
@@ -19,5 +19,5 @@
declare double @fabs(double) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/bit-extract.ll b/llvm/test/CodeGen/Hexagon/bit-extract.ll
index ad7d05d..33fa50c 100644
--- a/llvm/test/CodeGen/Hexagon/bit-extract.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-extract.ll
@@ -72,4 +72,4 @@
ret i32 %bf.ashr
}
-attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/bit-has.ll b/llvm/test/CodeGen/Hexagon/bit-has.ll
index 9022de3..5bb0f2f 100644
--- a/llvm/test/CodeGen/Hexagon/bit-has.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-has.ll
@@ -60,5 +60,5 @@
declare i32 @llvm.hexagon.A2.sath(i32) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
index db57998..e7dd87c 100644
--- a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
@@ -24,7 +24,7 @@
declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2
declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2
-attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { optsize }
diff --git a/llvm/test/CodeGen/Hexagon/bit-rie.ll b/llvm/test/CodeGen/Hexagon/bit-rie.ll
index 302382a..a090a66 100644
--- a/llvm/test/CodeGen/Hexagon/bit-rie.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-rie.ll
@@ -190,7 +190,7 @@
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
index c090721..a89a15c 100644
--- a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
+++ b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
@@ -24,4 +24,4 @@
attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
index 1d06953..7efc38f 100644
--- a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
+++ b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
@@ -17,5 +17,5 @@
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/builtin-expect.ll b/llvm/test/CodeGen/Hexagon/builtin-expect.ll
index 9945da1..9fed287 100644
--- a/llvm/test/CodeGen/Hexagon/builtin-expect.ll
+++ b/llvm/test/CodeGen/Hexagon/builtin-expect.ll
@@ -39,6 +39,6 @@
declare i32 @bar(i32) local_unnamed_addr #0
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" }
!0 = !{!"branch_weights", i32 1, i32 2000}
diff --git a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
index be234aa..2d65a5c 100644
--- a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
+++ b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
@@ -68,4 +68,4 @@
unreachable
}
-attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/cfi-offset.ll b/llvm/test/CodeGen/Hexagon/cfi-offset.ll
index 100034a0..c7d447d 100644
--- a/llvm/test/CodeGen/Hexagon/cfi-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/cfi-offset.ll
@@ -39,5 +39,5 @@
declare void @__cxa_end_catch()
-attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
index a8b7572..ddc73c2 100644
--- a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
+++ b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
@@ -17,4 +17,4 @@
ret i16 %a
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
index 9a4569b..e678925 100644
--- a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
+++ b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s
+; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
-; CHECK: @PCREL
+; CHECK: jumpr
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf"
diff --git a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
index b793fa0..c4e67f3 100644
--- a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
+++ b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
@@ -103,8 +103,8 @@
declare i32 @llvm.hexagon.A2.aslh(i32) #2
declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3
-attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind readnone }
-attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
attributes #4 = { nounwind optsize }
diff --git a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
index 35c12f1..62beeee 100644
--- a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
+++ b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
@@ -14,4 +14,4 @@
declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>)
declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>)
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll
index 0d8124e..532c2b2 100644
--- a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll
+++ b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
+; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s
; CHECK: ParseFunc:
; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])
; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]
@@ -126,6 +126,7 @@
; Function Attrs: nounwind
declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1
-attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
+
diff --git a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
index f45058f..ab8b00d 100644
--- a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
@@ -82,7 +82,7 @@
declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
-attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone }
!0 = !{!1, !1, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
index 6f3ec2d..6fd2aa1 100644
--- a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
+++ b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
@@ -66,4 +66,4 @@
ret void
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
index ca119e1..0507433 100644
--- a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
+++ b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
@@ -31,7 +31,7 @@
declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
index b3a4a2f..4c93ab2 100644
--- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
+++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
@@ -139,5 +139,5 @@
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
index ce7f5e0..350b0ed 100644
--- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
@@ -51,4 +51,4 @@
ret void
}
-attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
index ecec836..dbcba1a 100644
--- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
@@ -42,4 +42,4 @@
br label %b1
}
-attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll
index 1d07859..a5769db 100644
--- a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll
@@ -48,6 +48,6 @@
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #2 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
index 8524bf3..88eaec9 100644
--- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
@@ -91,5 +91,5 @@
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
-attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #3 = { nobuiltin nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
index 4f2bb86..641d53c 100644
--- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
@@ -210,7 +210,7 @@
br i1 %v146, label %b33, label %b34
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
attributes #3 = { nobuiltin nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll
index 1234baf..b9743ad 100644
--- a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll
+++ b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll
@@ -76,4 +76,4 @@
br i1 %v23, label %b13, label %b10
}
-attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/fminmax.ll b/llvm/test/CodeGen/Hexagon/fminmax.ll
index 7c1a9fb..cf1dc6c 100644
--- a/llvm/test/CodeGen/Hexagon/fminmax.ll
+++ b/llvm/test/CodeGen/Hexagon/fminmax.ll
@@ -22,6 +22,6 @@
declare float @fminf(float, float) #0
declare float @fmaxf(float, float) #0
-attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
index 43d5fd5..88d4e28 100644
--- a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
+++ b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
@@ -156,7 +156,7 @@
declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0
attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll
index 1154a71..f96eafe 100644
--- a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll
+++ b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll
@@ -18,7 +18,7 @@
; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
-attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" }
+attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone speculatable }
!llvm.dbg.cu = !{!0}
diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll
index c8b4994..c454a9f 100644
--- a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll
+++ b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll
@@ -19,7 +19,7 @@
; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
-attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" }
+attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-long-calls" }
attributes #1 = { nounwind readnone speculatable }
!llvm.dbg.cu = !{!0}
diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
index 1719003..ca1ba2f 100644
--- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
+++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
@@ -73,7 +73,7 @@
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1
-attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
!llvm.ident = !{!0}
diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll
index 3808364..8fb62b3 100644
--- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll
+++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll
@@ -73,7 +73,7 @@
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1
-attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
!llvm.ident = !{!0}
diff --git a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll
index 98c5ef4..38e597d 100644
--- a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll
+++ b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll
@@ -20,7 +20,7 @@
ret void
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll
index 1045e2e..accf6fd 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll
@@ -58,6 +58,6 @@
declare void @trap() #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
attributes #1 = { nounwind noreturn }
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
index e92461f..fb7e768 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
@@ -41,4 +41,4 @@
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" }
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
index 2563421..d540c09 100644
--- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
@@ -15,5 +15,5 @@
ret void
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
index 234f5a0..7d2f50e 100644
--- a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
@@ -12,4 +12,4 @@
ret void
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
index 2a54bfe..3b853eb 100644
--- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s
+; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq_128B
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
index 208c15f..5ff6722 100644
--- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s
+; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll
index 23473c9..1a5fd13 100644
--- a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll
@@ -65,7 +65,7 @@
declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2
declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
attributes #2 = { nounwind }
attributes #3 = { argmemonly nounwind writeonly }
diff --git a/llvm/test/CodeGen/Hexagon/jt-in-text.ll b/llvm/test/CodeGen/Hexagon/jt-in-text.ll
index 62b5cae..7389c960 100644
--- a/llvm/test/CodeGen/Hexagon/jt-in-text.ll
+++ b/llvm/test/CodeGen/Hexagon/jt-in-text.ll
@@ -54,4 +54,4 @@
ret void
}
-attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
index f738282..92f3b60 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
@@ -80,4 +80,4 @@
br label %for.body405
}
-attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" }
+attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
index 9907ae7..3e1e39b 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
@@ -81,4 +81,4 @@
ret i16 %v5
}
-attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll
index 0c6e458..2451842 100644
--- a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll
@@ -24,4 +24,4 @@
ret void
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" }
diff --git a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
index ba67de9..09ca465 100644
--- a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
+++ b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
@@ -43,5 +43,5 @@
; Function Attrs: nounwind readnone
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/memops-stack.ll b/llvm/test/CodeGen/Hexagon/memops-stack.ll
index 1aa2e30..9da319f 100644
--- a/llvm/test/CodeGen/Hexagon/memops-stack.ll
+++ b/llvm/test/CodeGen/Hexagon/memops-stack.ll
@@ -136,9 +136,9 @@
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
-attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #3 = { nounwind }
!1 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll
index 25cb14e..c147282 100644
--- a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll
+++ b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll
@@ -42,6 +42,6 @@
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll
index fc02182..b8caef9 100644
--- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll
+++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll
@@ -95,7 +95,7 @@
declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
!1 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/newify-crash.ll b/llvm/test/CodeGen/Hexagon/newify-crash.ll
index 705170b..bb29954 100644
--- a/llvm/test/CodeGen/Hexagon/newify-crash.ll
+++ b/llvm/test/CodeGen/Hexagon/newify-crash.ll
@@ -40,5 +40,5 @@
declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1
declare void @f0() #0
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll
index 1e2e6c2..9347966 100644
--- a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll
+++ b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll
@@ -74,6 +74,6 @@
}
attributes #0 = { argmemonly nounwind }
-attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" }
-attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" }
+attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
+attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll
index 03de153..4a24ea6 100644
--- a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll
+++ b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll
@@ -23,5 +23,5 @@
ret void
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
diff --git a/llvm/test/CodeGen/Hexagon/plt-rel.ll b/llvm/test/CodeGen/Hexagon/plt-rel.ll
index 1d38cf3..d1d97a6 100644
--- a/llvm/test/CodeGen/Hexagon/plt-rel.ll
+++ b/llvm/test/CodeGen/Hexagon/plt-rel.ll
@@ -34,4 +34,4 @@
ret i1 %.sink
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
diff --git a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
index fb2f038..673a9b4 100644
--- a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
+++ b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
@@ -29,7 +29,7 @@
ret void
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
!1 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll
index 4948a89..989322a 100644
--- a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll
+++ b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll
@@ -42,7 +42,7 @@
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
-attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" }
-attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
+attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll
index 3d65968..91aec77 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll
@@ -48,5 +48,5 @@
declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1
declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1
-attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
index 222d8a2..d06da93 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
@@ -26,7 +26,7 @@
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
index ae090626..2661f8c 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll
@@ -24,7 +24,7 @@
ret i32 %retval1.0
}
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
!1 = !{i32 155}
diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll
index db9ed55..c73d4c7 100644
--- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll
+++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s
+; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vmem
diff --git a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
index 78c4b98..bc878e0 100644
--- a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
+++ b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
@@ -95,6 +95,6 @@
ret void
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index a541e76..7e18011 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -58,7 +58,7 @@
declare i32 @lrand48() #0
declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1
- attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double" }
+ attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx" }
attributes #1 = { nounwind readnone }
...
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll
index c98fcb6..2dc9a7a 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll
+++ b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll
@@ -138,6 +138,6 @@
br label %b39
}
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/select-instr-align.ll b/llvm/test/CodeGen/Hexagon/select-instr-align.ll
index e3b2929..368ee3c 100644
--- a/llvm/test/CodeGen/Hexagon/select-instr-align.ll
+++ b/llvm/test/CodeGen/Hexagon/select-instr-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK-LABEL: aligned_load:
; CHECK: = vmem({{.*}})
; CHECK-LABEL: aligned_store:
diff --git a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll
index 0d028fb..f7639c7 100644
--- a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll
+++ b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll
@@ -47,5 +47,5 @@
declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/store-shift.ll b/llvm/test/CodeGen/Hexagon/store-shift.ll
index 981071a..f7bed98 100644
--- a/llvm/test/CodeGen/Hexagon/store-shift.ll
+++ b/llvm/test/CodeGen/Hexagon/store-shift.ll
@@ -42,7 +42,7 @@
ret void
}
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll
index 6c67a0d..b80e8e3 100644
--- a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll
+++ b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll
@@ -29,4 +29,4 @@
ret i32 19
}
-attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll
index bb2b1e7..542bfbb 100644
--- a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll
+++ b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll
@@ -27,4 +27,4 @@
ret i32 19
}
-attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll
index 57fdfbf..22b61f0 100644
--- a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll
+++ b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll
@@ -39,4 +39,4 @@
ret i32 19
}
-attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll
index b4d3e89..203ea4a 100644
--- a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll
+++ b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll
@@ -24,4 +24,4 @@
ret i32 19
}
-attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll
index c1ab5d7..5aa7f39 100644
--- a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll
+++ b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll
@@ -54,6 +54,6 @@
ret void
}
-attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
-attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
+attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/v60-cur.ll b/llvm/test/CodeGen/Hexagon/v60-cur.ll
index a7d4f6d..26d40c9 100644
--- a/llvm/test/CodeGen/Hexagon/v60-cur.ll
+++ b/llvm/test/CodeGen/Hexagon/v60-cur.ll
@@ -54,7 +54,7 @@
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
!1 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll
index e673145..71d112c 100644
--- a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll
+++ b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll
@@ -65,5 +65,5 @@
declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/v60Intrins.ll b/llvm/test/CodeGen/Hexagon/v60Intrins.ll
index d0064c5..980d870 100644
--- a/llvm/test/CodeGen/Hexagon/v60Intrins.ll
+++ b/llvm/test/CodeGen/Hexagon/v60Intrins.ll
@@ -2555,5 +2555,5 @@
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/v60Vasr.ll b/llvm/test/CodeGen/Hexagon/v60Vasr.ll
index fb177f6..dd309f6 100644
--- a/llvm/test/CodeGen/Hexagon/v60Vasr.ll
+++ b/llvm/test/CodeGen/Hexagon/v60Vasr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s
+; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat
diff --git a/llvm/test/CodeGen/Hexagon/v60small.ll b/llvm/test/CodeGen/Hexagon/v60small.ll
index 8a6a615..efa726e 100644
--- a/llvm/test/CodeGen/Hexagon/v60small.ll
+++ b/llvm/test/CodeGen/Hexagon/v60small.ll
@@ -47,5 +47,5 @@
; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
index 24daeac..18c2cf6 100644
--- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
+++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck %s
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
; generate .long XXXX which is a vector debug print instruction.
; CHECK: .long 0x1dffe0
; CHECK: .long 0x1dffe0
diff --git a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
index a9a0d51..0facdc3 100644
--- a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
+++ b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
@@ -52,5 +52,5 @@
}
attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
index 7e41bd4..352398e 100644
--- a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
+++ b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
@@ -155,8 +155,8 @@
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!5 = !{!6, !6, i64 0}
!6 = !{!"inputOne", !7}
diff --git a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
index d120295..40b4a81 100644
--- a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
+++ b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
; CHECK: call puts
diff --git a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
index d4c6bd3..0101c1f 100644
--- a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
+++ b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
@@ -27,4 +27,4 @@
declare i32 @printf(i8*, ...) #0
declare void @VarVec1(i8*, i32, ...) #0
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
diff --git a/llvm/test/CodeGen/Hexagon/vector-align.ll b/llvm/test/CodeGen/Hexagon/vector-align.ll
index 557ee3f..043839c 100644
--- a/llvm/test/CodeGen/Hexagon/vector-align.ll
+++ b/llvm/test/CodeGen/Hexagon/vector-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s \
; RUN: | FileCheck %s
; Check that the store to Q6VecPredResult does not get expanded into multiple
diff --git a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
index 70ed3a9b1..a3bed31 100644
--- a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
+++ b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
@@ -49,4 +49,4 @@
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
diff --git a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
index 9c35990..8b207ba 100644
--- a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
+++ b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
@@ -133,8 +133,8 @@
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!5 = !{!6, !6, i64 0}
!6 = !{!"inputOne", !7}
diff --git a/llvm/test/CodeGen/Hexagon/vpack_eo.ll b/llvm/test/CodeGen/Hexagon/vpack_eo.ll
index 7238ca8..cf8619c 100644
--- a/llvm/test/CodeGen/Hexagon/vpack_eo.ll
+++ b/llvm/test/CodeGen/Hexagon/vpack_eo.ll
@@ -61,8 +61,8 @@
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!4 = !{!5, !5, i64 0}
!5 = !{!"InputOne", !6}
diff --git a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
index ef86e47..e6be3ee 100644
--- a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
+++ b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s
+; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
; REQUIRES: asserts
target triple = "hexagon"