[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero-
extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both
operands have to be sign-/zero-extended with separate instructions.
Related to <rdar://problem/17913111>.
llvm-svn: 216073
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
index bd1666b..e0d7d41 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
@@ -172,6 +172,17 @@
ret i32 %conv2
}
+define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind {
+entry:
+; CHECK-LABEL: icmp_i1_signed
+; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1
+; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1
+; CHECK-NEXT: cmp [[REG1]], [[REG2]]
+; CHECK-NEXT: cset w0, gt
+ %cmp = icmp sgt i1 %a, %b
+ %conv2 = zext i1 %cmp to i32
+ ret i32 %conv2
+}
define i32 @icmp_i16_signed_const(i16 %a) nounwind {
entry: