commit e22f9181f7066b8c7d1cb797d41d0430181839d4
author Evan Cheng <evan.cheng@apple.com> Sat Dec 17 01:19:28 2005 +0000
committer Evan Cheng <evan.cheng@apple.com> Sat Dec 17 01:19:28 2005 +0000
tree 86ef786fb3ec3bbd9dddca20e61851ea4c9466cc
parent a93464d8ac7d5d49a96a36e58556306c14e95fb4

Support for read / write from explicit registers with FlagVT type.

llvm-svn: 24753

llvm/utils/TableGen/CodeGenTarget.cpp

diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index b16bc88..c06b73f 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -45,6 +45,7 @@
   case MVT::f64:   return "f64";
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
+  case MVT::Flag:  return "Flag";
   case MVT::isVoid:return "void";
   case MVT::v16i8: return "v16i8";
   case MVT::v8i16: return "v8i16";
@@ -69,6 +70,7 @@
   case MVT::f64:   return "f64";
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
+  case MVT::Flag:  return "Flag";
   case MVT::isVoid:return "isVoid";
   case MVT::v16i8: return "v16i8";
   case MVT::v8i16: return "v8i16";