commit e26118473eb422a6a4dea733108d54e170aaba2c
author Craig Topper <craig.topper@intel.com> Wed Mar 21 05:13:04 2018 +0000
committer Craig Topper <craig.topper@intel.com> Wed Mar 21 05:13:04 2018 +0000
tree cdd98751f7d77b2d7a455dedb212f8a7f0ef79b8
parent 6f2cc9b107d2b9807657fed49570e726f344ae96

[TableGen] Remove a defaulted function argument that is never called with another value. NFC

llvm-svn: 328075

llvm/utils/TableGen/CodeGenSchedule.cpp

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 09e41e7..8f51df8 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -405,11 +405,9 @@
   return Name;
 }
 
-unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
-                                           unsigned After) const {
+unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead) const {
   const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
-  assert(After < RWVec.size() && "start position out of bounds");
-  for (std::vector<CodeGenSchedRW>::const_iterator I = RWVec.begin() + After,
+  for (std::vector<CodeGenSchedRW>::const_iterator I = RWVec.begin(),
          E = RWVec.end(); I != E; ++I) {
     if (I->TheDef == Def)
       return I - RWVec.begin();

llvm/utils/TableGen/CodeGenSchedule.h

diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h
index dcadacc..59c084b 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/CodeGenSchedule.h
@@ -336,7 +336,7 @@
     return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
   }
 
-  unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
+  unsigned getSchedRWIdx(Record *Def, bool IsRead) const;
 
   // Return true if the given write record is referenced by a ReadAdvance.
   bool hasReadOfWrite(Record *WriteDef) const;