AMDGPU: Add f16 to shader calling conventions
Mostly useful for writing tests for f16 features.
llvm-svn: 296370
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 57adc8be..55c2b50 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -1,9 +1,10 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Make sure we don't crash or assert on spir_kernel calling convention.
-; SI-LABEL: {{^}}kernel:
-; SI: s_endpgm
+; GCN-LABEL: {{^}}kernel:
+; GCN: s_endpgm
define spir_kernel void @kernel(i32 addrspace(1)* %out) {
entry:
store i32 0, i32 addrspace(1)* %out
@@ -11,10 +12,34 @@
}
; FIXME: This is treated like a kernel
-; SI-LABEL: {{^}}func:
-; SI: s_endpgm
+; GCN-LABEL: {{^}}func:
+; GCN: s_endpgm
define spir_func void @func(i32 addrspace(1)* %out) {
entry:
store i32 0, i32 addrspace(1)* %out
ret void
}
+
+; GCN-LABEL: {{^}}ps_ret_cc_f16:
+; SI: v_cvt_f16_f32_e32 v0, v0
+; SI: v_cvt_f32_f16_e32 v0, v0
+; SI: v_add_f32_e32 v0, 1.0, v0
+
+; VI: v_add_f16_e32 v0, 1.0, v0
+; VI: ; return
+define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
+ %add = fadd half %arg0, 1.0
+ ret half %add
+}
+
+; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16:
+; SI: v_cvt_f16_f32_e32 v0, s0
+; SI: v_cvt_f32_f16_e32 v0, v0
+; SI: v_add_f32_e32 v0, 1.0, v0
+
+; VI: v_add_f16_e64 v0, s0, 1.0
+; VI: ; return
+define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
+ %add = fadd half %arg0, 1.0
+ ret half %add
+}