Enable generation of AssertSext and AssertZext in the PPC backend.
llvm-svn: 23168
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index dad4c9f..fd9233f2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -214,8 +214,13 @@
MF.addLiveIn(GPR[GPR_idx]);
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
GPR[GPR_idx], MVT::i32);
- if (ObjectVT != MVT::i32)
- argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
+ if (ObjectVT != MVT::i32) {
+ unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
+ : ISD::AssertZext;
+ argt = DAG.getNode(AssertOp, MVT::i32, argt,
+ DAG.getValueType(ObjectVT));
+ argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
+ }
} else {
needsLoad = true;
}