commit e373163e951f4c8a4d44e4aae8edbaff8f7bdf14
author Andrew Lenharth <andrewl@lenharth.org> Thu Nov 10 16:59:55 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Thu Nov 10 16:59:55 2005 +0000
tree 53aef58d0bd25af6495f9786aa8a38bc61e612ae
parent 3d3de4e6c3c30e22047552654fd83f8a25682a4a

fix a bunch of regressions

llvm-svn: 24269

llvm/lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 96684ba..eb13486 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1295,11 +1295,11 @@
       if (SrcType == MVT::f32)
         {
           Tmp2 = MakeReg(MVT::f64);
-          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
           Tmp1 = Tmp2;
         }
       Tmp2 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
       MoveFP2Int(Tmp2, Result, true);
 
       return Result;