Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
llvm-svn: 23654
diff --git a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
index dc84075..2af1099 100644
--- a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
@@ -57,7 +57,8 @@
destReg = MI.getOperand(0).getReg();
return true;
}
- } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2
+ } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
+ oc == PPC::FMRSD) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&