CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().
llvm-svn: 364191
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h
index 5ac81e2..0e18ac8 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h
@@ -124,7 +124,7 @@
return MF;
}
-static void collectCopies(SmallVectorImpl<unsigned> &Copies,
+static void collectCopies(SmallVectorImpl<Register> &Copies,
MachineFunction *MF) {
for (auto &MBB : *MF)
for (MachineInstr &MI : MBB) {
@@ -152,7 +152,7 @@
MachineFunction *MF;
std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
ModuleMMIPair;
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
MachineBasicBlock *EntryMBB;
MachineIRBuilder B;
MachineRegisterInfo *MRI;
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
index a61cb56..f6d8112 100644
--- a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
@@ -75,7 +75,7 @@
if (!TM)
return;
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
LLT s64 = LLT::scalar(64);
@@ -100,7 +100,7 @@
if (!TM)
return;
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
B.buildUnmerge(LLT::scalar(32), Copies[0]);
B.buildUnmerge(LLT::scalar(16), Copies[1]);
@@ -120,7 +120,7 @@
if (!TM)
return;
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
LLT S64 = LLT::scalar(64);
@@ -152,7 +152,7 @@
return;
LLT S64 = LLT::scalar(64);
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
// Make sure DstOp version works. sqrt is just a placeholder intrinsic.
@@ -160,7 +160,7 @@
.addUse(Copies[0]);
// Make sure register version works
- SmallVector<unsigned, 1> Results;
+ SmallVector<Register, 1> Results;
Results.push_back(MRI->createGenericVirtualRegister(S64));
B.buildIntrinsic(Intrinsic::sqrt, Results, false)
.addUse(Copies[1]);
@@ -181,7 +181,7 @@
LLT S64 = LLT::scalar(64);
LLT S128 = LLT::scalar(128);
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
B.buildXor(S64, Copies[0], Copies[1]);
B.buildNot(S64, Copies[0]);
@@ -208,7 +208,7 @@
return;
LLT S32 = LLT::scalar(32);
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
B.buildCTPOP(S32, Copies[0]);
@@ -235,7 +235,7 @@
return;
LLT S32 = LLT::scalar(32);
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
B.buildUITOFP(S32, Copies[0]);
@@ -259,7 +259,7 @@
return;
LLT S64 = LLT::scalar(64);
- SmallVector<unsigned, 4> Copies;
+ SmallVector<Register, 4> Copies;
collectCopies(Copies, MF);
B.buildSMin(S64, Copies[0], Copies[1]);
diff --git a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
index f7dda96..aed0b3f 100644
--- a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
@@ -161,7 +161,7 @@
bool match =
mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg()));
EXPECT_TRUE(match);
- unsigned Src0, Src1, Src2;
+ Register Src0, Src1, Src2;
match = mi_match(MIBAdd->getOperand(0).getReg(), MRI,
m_GAdd(m_Reg(Src0), m_Reg(Src1)));
EXPECT_TRUE(match);
@@ -292,7 +292,7 @@
bool match = mi_match(MIBFabs->getOperand(0).getReg(), MRI, m_GFabs(m_Reg()));
EXPECT_TRUE(match);
- unsigned Src;
+ Register Src;
auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
match = mi_match(MIBFNeg->getOperand(0).getReg(), MRI, m_GFNeg(m_Reg(Src)));
EXPECT_TRUE(match);
@@ -360,7 +360,7 @@
auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
auto MIBZExt = B.buildZExt(s64, MIBTrunc);
auto MIBSExt = B.buildSExt(s64, MIBTrunc);
- unsigned Src0;
+ Register Src0;
bool match =
mi_match(MIBTrunc->getOperand(0).getReg(), MRI, m_GTrunc(m_Reg(Src0)));
EXPECT_TRUE(match);
@@ -433,7 +433,7 @@
LLT PtrTy = LLT::pointer(0, 64);
auto MIBIntToPtr = B.buildCast(PtrTy, Copies[0]);
auto MIBPtrToInt = B.buildCast(s64, MIBIntToPtr);
- unsigned Src0;
+ Register Src0;
// match the ptrtoint(inttoptr reg)
bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), MRI,
@@ -459,7 +459,7 @@
LLT s64 = LLT::scalar(64);
LLT s32 = LLT::scalar(32);
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
- unsigned Src0, Src1;
+ Register Src0, Src1;
bool match =
mi_match(MIBAdd->getOperand(0).getReg(), MRI,
m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1))));