Disabled subregister copy coalescing during MachineCSE.
This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.
llvm-svn: 197514
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 80982bc..35ba7ff 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -133,16 +133,26 @@
continue;
if (DefMI->getOperand(0).getSubReg())
continue;
- unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
+ // FIXME: We should trivially coalesce subregister copies to expose CSE
+ // opportunities on instructions with truncated operands (see
+ // cse-add-with-overflow.ll). This can be done here as follows:
+ // if (SrcSubReg)
+ // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
+ // SrcSubReg);
+ // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+ //
+ // The 2-addr pass has been updated to handle coalesced subregs. However,
+ // some machine-specific code still can't handle it.
+ // To handle it properly we also need a way find a constrained subregister
+ // class given a super-reg class and subreg index.
+ if (DefMI->getOperand(1).getSubReg())
+ continue;
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- if (SrcSubReg)
- RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
- SrcSubReg);
if (!MRI->constrainRegClass(SrcReg, RC))
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
- MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+ MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
DefMI->eraseFromParent();
++NumCoalesces;