partial implementation of the ARM Addressing Mode 1
llvm-svn: 30252
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 4384c28..da1479c 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -33,15 +33,15 @@
unsigned &SrcReg, unsigned &DstReg) const {
MachineOpCode oc = MI.getOpcode();
switch (oc) {
- default:
- return false;
- case ARM::movrr:
+ case ARM::MOV:
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
- SrcReg = MI.getOperand(1).getReg();;
- DstReg = MI.getOperand(0).getReg();;
- return true;
+ if (MI.getOperand(1).isRegister()) {
+ SrcReg = MI.getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ return true;
+ }
}
+ return false;
}