commit e5147247b8cea11e06225e1ee27a5ed4af57824f
author Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Fri Apr 07 13:07:13 2017 +0000
committer Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Fri Apr 07 13:07:13 2017 +0000
tree 600731e324cb24dab0b96c0310b23e4f15029813
parent 6470ff0b24271cd0890bb56366dd7dc4cab4de06

[AMDGPU][MC] Fix for Bug 28211 + LIT tests

- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description)
  - address operand is not used
  - several opcodes have data operand
  - all opcodes have offset modifier
- DS_AND_SRC2_B32: corrected typo in mnemo
- DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32
- added CI/VI opcodes:
  - DS_CONDXCHG32_RTN_B64
  - DS_GWS_SEMA_RELEASE_ALL
- added VI opcodes:
  - DS_CONSUME
  - DS_APPEND
  - DS_ORDERED_COUNT

Differential Revision: https://reviews.llvm.org/D31707

llvm-svn: 299767