revert r117858 while I check out a failure I missed.
llvm-svn: 117859
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index f2ed162..65fb12e 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -257,26 +257,27 @@
// this implies a constraint we would not honor.
std::set<std::string> OperandNames;
for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
- for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
- if (Tokens[i][0] == '$' &&
- Tokens[i].find(':') != StringRef::npos) {
- PrintError(CGI.TheDef->getLoc(),
- "instruction with operand modifier '" + Tokens[i].str() +
- "' not supported by asm matcher. Mark isCodeGenOnly!");
- throw std::string("ERROR: Invalid instruction");
- }
-
- if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
- DEBUG({
+ if (Tokens[i][0] == '$' &&
+ std::find(Tokens[i].begin(),
+ Tokens[i].end(), ':') != Tokens[i].end()) {
+ DEBUG({
+ errs() << "warning: '" << Name << "': "
+ << "ignoring instruction; operand with attribute '"
+ << Tokens[i] << "'\n";
+ });
+ return false;
+ }
+
+ if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
+ DEBUG({
errs() << "warning: '" << Name << "': "
<< "ignoring instruction with tied operand '"
<< Tokens[i].str() << "'\n";
});
- return false;
- }
+ return false;
}
}
-
+
return true;
}
@@ -647,11 +648,13 @@
case '*': Res += "_STAR_"; break;
case '%': Res += "_PCT_"; break;
case ':': Res += "_COLON_"; break;
+
default:
- if (isalnum(*it))
+ if (isalnum(*it)) {
Res += *it;
- else
+ } else {
Res += "_" + utostr((unsigned) *it) + "_";
+ }
}
}
@@ -901,6 +904,14 @@
}
void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
+ // Parse the instructions; we need to do this first so that we can gather the
+ // singleton register classes.
+ std::set<std::string> SingletonRegisterNames;
+
+ const std::vector<const CodeGenInstruction*> &InstrList =
+ Target.getInstructionsByEnumValue();
+
+
// Build information about all of the AssemblerPredicates.
std::vector<Record*> AllPredicates =
Records.getAllDerivedDefinitions("Predicate");
@@ -920,16 +931,9 @@
assert(FeatureNo < 32 && "Too many subtarget features!");
}
- // Parse the instructions; we need to do this first so that we can gather the
- // singleton register classes.
- std::set<std::string> SingletonRegisterNames;
- const std::vector<const CodeGenInstruction*> &InstrList =
- Target.getInstructionsByEnumValue();
for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
const CodeGenInstruction &CGI = *InstrList[i];
- // If the tblgen -match-prefix option is specified (for tblgen hackers),
- // filter the set of instructions we consider.
if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
continue;
@@ -939,8 +943,7 @@
II->Instr = &CGI;
II->AsmString = FlattenVariants(CGI.AsmString, 0);
- // Remove comments from the asm string. We know that the asmstring only
- // has one line.
+ // Remove comments from the asm string.
if (!CommentDelimiter.empty()) {
size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
if (Idx != StringRef::npos)
@@ -952,7 +955,7 @@
// Ignore instructions which shouldn't be matched.
if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens))
continue;
-
+
// Collect singleton registers, if used.
for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
if (!II->Tokens[i].startswith(RegisterPrefix))