commit e5b5d8fbb3390246de5d2110dfb7fca5f597d65c
author David Goodwin <david_goodwin@apple.com> Wed Aug 05 21:02:22 2009 +0000
committer David Goodwin <david_goodwin@apple.com> Wed Aug 05 21:02:22 2009 +0000
tree 8488e4723985a36a8dc30a339c7bb81727890dab
parent fdd2519eb5cb5615d25bd61817020f75845d7f77

When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.

llvm-svn: 78244

llvm/lib/Target/ARM/ARMInstrNEON.td

diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 5cf81ee..d31ec41 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -285,9 +285,11 @@
 // Basic 2-register operations, scalar single-precision
 class N2VDInts<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a)),
-              (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                     SPR:$a, arm_ssubreg_0)),
-              arm_ssubreg_0)>;
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS 
+                  (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 
+                                        SPR:$a, arm_ssubreg_0)),
+                               DPR_VFP2),
+               arm_ssubreg_0)>;
 
 // Narrow 2-register intrinsics.
 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
@@ -329,11 +331,13 @@
 // Basic 3-register operations, scalar single-precision
 class N3VDs<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
-              (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$a, arm_ssubreg_0),
-                                    (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$b, arm_ssubreg_0)),
-              arm_ssubreg_0)>;
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS
+                  (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
+                                        SPR:$a, arm_ssubreg_0),
+                        (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
+                                        SPR:$b, arm_ssubreg_0)),
+                               DPR_VFP2),
+               arm_ssubreg_0)>;
 
 // Basic 3-register intrinsics, both double- and quad-register.
 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -375,12 +379,14 @@
 class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$acc, 
                        (f32 (MulNode SPR:$a, SPR:$b)))),
-              (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$acc, arm_ssubreg_0),
-                                    (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$a, arm_ssubreg_0),
-                                    (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$b, arm_ssubreg_0)),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS
+                  (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
+                                        SPR:$acc, arm_ssubreg_0),
+                        (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
+                                        SPR:$a, arm_ssubreg_0),
+                        (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
+                                        SPR:$b, arm_ssubreg_0)),
+                               DPR_VFP2),
                arm_ssubreg_0)>;
 
 // Neon 3-argument intrinsics, both double- and quad-register.