commit e5ce7090228aa49732d17c827d76ec9f4e6b9778
author Akira Hatanaka <ahatanak@gmail.com> Mon Sep 26 21:37:50 2011 +0000
committer Akira Hatanaka <ahatanak@gmail.com> Mon Sep 26 21:37:50 2011 +0000
tree 248c6e38f46e58a801555e76d8d94b7ea145dd4c
parent ab7b99ab9cdd337ce44859ceaf77efa440704350

In single float mode, double precision FP arguments are passed in integer
registers, so there is no need to check here.

llvm-svn: 140568

llvm/lib/Target/Mips/MipsISelLowering.cpp

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 77650c7..130e359 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -2267,10 +2267,9 @@
         RC = Mips::CPU64RegsRegisterClass;
       else if (RegVT == MVT::f32)
         RC = Mips::FGR32RegisterClass;
-      else if (RegVT == MVT::f64) {
-        if (!Subtarget->isSingleFloat())
-          RC = Mips::AFGR64RegisterClass;
-      } else
+      else if (RegVT == MVT::f64)
+        RC = Mips::AFGR64RegisterClass;
+      else
         llvm_unreachable("RegVT not supported by FormalArguments Lowering");
 
       // Transform the arguments stored on