TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC
llvm-svn: 248623
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index ba1f571..507729a 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -263,7 +263,7 @@
SlotIndex MBBBegin = MBBI->first;
// Advance all subrange iterators so that their end position is just
// behind MBBBegin (or the iterator is at the end).
- unsigned LaneMask = 0;
+ LaneBitmask LaneMask = 0;
for (auto &RangeIterPair : SubRanges) {
const LiveInterval::SubRange *SR = RangeIterPair.first;
LiveInterval::const_iterator &SRI = RangeIterPair.second;
@@ -335,7 +335,7 @@
assert(LI.liveAt(BaseIndex) &&
"Reads of completely dead register should be marked undef already");
unsigned SubRegIdx = MO.getSubReg();
- unsigned UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
+ LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
// See if any of the relevant subregister liveranges is defined at this point.
for (const LiveInterval::SubRange &SR : LI.subranges()) {
if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
@@ -405,7 +405,7 @@
// our subregister liveness tracking isn't precise and we can't
// know what subregister parts are undefined, fall back to the
// implicit super-register def then.
- unsigned LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
+ LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
if (TargetRegisterInfo::isImpreciseLaneMask(LaneMask))
SuperDefs.push_back(PhysReg);
}