commit e7b2a864f2441905d1f9bf46e7bb81f4732d80bc
author Bill Wendling <isanbard@gmail.com> Tue Apr 03 06:00:37 2007 +0000
committer Bill Wendling <isanbard@gmail.com> Tue Apr 03 06:00:37 2007 +0000
tree 60f7756e3bb22e6a2a0ee553cc991fea855613eb
parent 81e0707552bdb5e9402c03501779977074002e46

Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.

llvm-svn: 35616

llvm/lib/Target/X86/X86InstrInfo.cpp

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3809b80..1a0ffed 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -38,7 +38,7 @@
       oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
       oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
       oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
-      oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
+      oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
@@ -65,8 +65,8 @@
   case X86::MOVSDrm:
   case X86::MOVAPSrm:
   case X86::MOVAPDrm:
-  case X86::MOVD64rm:
-  case X86::MOVQ64rm:
+  case X86::MMX_MOVD64rm:
+  case X86::MMX_MOVQ64rm:
     if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
         MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
         MI->getOperand(2).getImmedValue() == 1 &&
@@ -95,8 +95,8 @@
   case X86::MOVSDmr:
   case X86::MOVAPSmr:
   case X86::MOVAPDmr:
-  case X86::MOVD64mr:
-  case X86::MOVQ64mr:
+  case X86::MMX_MOVD64mr:
+  case X86::MMX_MOVQ64mr:
     if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
         MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
         MI->getOperand(1).getImmedValue() == 1 &&