commit	e85b06d65f695c576df1e529ee37cb15e6902401	[log] [tgz]
author	Francis Visoiu Mistrih <francisvm@yahoo.com>	Wed Mar 14 21:52:13 2018 +0000
committer	Francis Visoiu Mistrih <francisvm@yahoo.com>	Wed Mar 14 21:52:13 2018 +0000
tree	8cc427373ec791f148ac34dd3f8153e4b6727aed
parent	ca5cc20e5163f0ee16a51832ac21ed5d6d20529f [diff]

[CodeGen] Use MIR syntax for MachineMemOperand printing

Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)".

rdar://38163529

Differential Revision: https://reviews.llvm.org/D42377

llvm-svn: 327580

llvm/include/llvm/CodeGen/MachineMemOperand.h[diff]
llvm/lib/CodeGen/MIRPrinter.cpp[diff]
llvm/lib/CodeGen/MachineInstr.cpp[diff]
llvm/lib/CodeGen/MachineOperand.cpp[diff]
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp[diff]
llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll[diff]
llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll[diff]
llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll[diff]
llvm/test/CodeGen/AMDGPU/extload-align.ll[diff]
llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll[diff]
llvm/test/CodeGen/ARM/ldrd-memoper.ll[diff]
llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir[diff]
llvm/test/CodeGen/ARM/single-issue-r52.mir[diff]
llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll[diff]
llvm/test/CodeGen/PowerPC/byval-agg-info.ll[diff]
llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll[diff]
llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll[diff]
llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll[diff]
llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll[diff]
llvm/test/CodeGen/X86/stack-protector-weight.ll[diff]

20 files changed

tree: 8cc427373ec791f148ac34dd3f8153e4b6727aed

clang/
clang-tools-extra/
compiler-rt/
debuginfo-tests/
libclc/
libcxx/
libcxxabi/
libunwind/
lld/
lldb/
llgo/
llvm/
openmp/
parallel-libs/
polly/
README.md

README.md

Low Level Virtual Machine (LLVM)

This directory and its subdirectories contain source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and runtime environments.