MC: Modernize MCOperand API naming. NFC.
MCOperand::Create*() methods renamed to MCOperand::create*().
llvm-svn: 237275
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index b4e0791..77e2600 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1334,7 +1334,7 @@
case ARM::t2MOVi16_ga_pcrel: {
MCInst TmpInst;
TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
unsigned TF = MI->getOperand(1).getTargetFlags();
const GlobalValue *GV = MI->getOperand(1).getGlobal();
@@ -1351,13 +1351,13 @@
MCBinaryExpr::CreateAdd(LabelSymExpr,
MCConstantExpr::Create(PCAdj, OutContext),
OutContext), OutContext), OutContext);
- TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
+ TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -1366,8 +1366,8 @@
MCInst TmpInst;
TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
? ARM::MOVTi16 : ARM::t2MOVTi16);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
unsigned TF = MI->getOperand(2).getTargetFlags();
const GlobalValue *GV = MI->getOperand(2).getGlobal();
@@ -1384,12 +1384,12 @@
MCBinaryExpr::CreateAdd(LabelSymExpr,
MCConstantExpr::Create(PCAdj, OutContext),
OutContext), OutContext), OutContext);
- TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
+ TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -1557,14 +1557,14 @@
unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
ARM::MOVr : ARM::tMOVr;
TmpInst.setOpcode(Opc);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
if (Opc == ARM::MOVr)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
// Make sure the Thumb jump table is 4-byte aligned.
@@ -1582,19 +1582,19 @@
if (MI->getOperand(1).getReg() == 0) {
// literal offset
TmpInst.setOpcode(ARM::LDRi12);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
} else {
TmpInst.setOpcode(ARM::LDRrs);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
+ TmpInst.addOperand(MCOperand::createImm(0));
}
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
// Output the data for the jump table itself
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 7c004c9..84f95be 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -36,16 +36,16 @@
void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
if (hasNOP()) {
NopInst.setOpcode(ARM::HINT);
- NopInst.addOperand(MCOperand::CreateImm(0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createImm(0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
} else {
NopInst.setOpcode(ARM::MOVr);
- NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
- NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
+ NopInst.addOperand(MCOperand::createReg(0));
}
}
diff --git a/llvm/lib/Target/ARM/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
index fd4f5ff..e370b96 100644
--- a/llvm/lib/Target/ARM/ARMMCInstLower.cpp
+++ b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
@@ -61,7 +61,7 @@
MCConstantExpr::Create(MO.getOffset(),
OutContext),
OutContext);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
@@ -74,13 +74,13 @@
if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!");
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), OutContext));
break;
case MachineOperand::MO_GlobalAddress: {
@@ -105,7 +105,7 @@
APFloat Val = MO.getFPImm()->getValueAPF();
bool ignored;
Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
- MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
+ MCOp = MCOperand::createFPImm(Val.convertToDouble());
break;
}
case MachineOperand::MO_RegisterMask:
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 66be62d..fed92aa 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1749,62 +1749,62 @@
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
- Inst.addOperand(MCOperand::CreateReg(RegNum));
+ Inst.addOperand(MCOperand::createReg(RegNum));
}
void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCoproc()));
+ Inst.addOperand(MCOperand::createImm(getCoproc()));
}
void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCoproc()));
+ Inst.addOperand(MCOperand::createImm(getCoproc()));
}
void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
+ Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
}
void addITMaskOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
+ Inst.addOperand(MCOperand::createImm(ITMask.Mask));
}
void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
}
void addCCOutOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
assert(isRegShiftedReg() &&
"addRegShiftedRegOperands() on non-RegShiftedReg!");
- Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
- Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
- Inst.addOperand(MCOperand::CreateImm(
+ Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
+ Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
+ Inst.addOperand(MCOperand::createImm(
ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
}
@@ -1812,16 +1812,16 @@
assert(N == 2 && "Invalid number of operands!");
assert(isRegShiftedImm() &&
"addRegShiftedImmOperands() on non-RegShiftedImm!");
- Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
+ Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
// Shift of #32 is encoded as 0 where permitted
unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
- Inst.addOperand(MCOperand::CreateImm(
+ Inst.addOperand(MCOperand::createImm(
ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
}
void addShifterImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
+ Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
ShifterImm.Imm));
}
@@ -1830,7 +1830,7 @@
const SmallVectorImpl<unsigned> &RegList = getRegList();
for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I)
- Inst.addOperand(MCOperand::CreateReg(*I));
+ Inst.addOperand(MCOperand::createReg(*I));
}
void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
@@ -1844,7 +1844,7 @@
void addRotImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Encoded as val>>3. The printer handles display as 8, 16, 24.
- Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
+ Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
}
void addModImmOperands(MCInst &Inst, unsigned N) const {
@@ -1854,21 +1854,21 @@
if (isImm())
return addImmOperands(Inst, N);
- Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
+ Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
}
void addModImmNotOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
- Inst.addOperand(MCOperand::CreateImm(Enc));
+ Inst.addOperand(MCOperand::createImm(Enc));
}
void addModImmNegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
- Inst.addOperand(MCOperand::CreateImm(Enc));
+ Inst.addOperand(MCOperand::createImm(Enc));
}
void addBitfieldOperands(MCInst &Inst, unsigned N) const {
@@ -1879,7 +1879,7 @@
// Make a 32-bit mask w/ the referenced bits clear and all other bits set.
uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
(32 - (lsb + width)));
- Inst.addOperand(MCOperand::CreateImm(Mask));
+ Inst.addOperand(MCOperand::createImm(Mask));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -1890,20 +1890,20 @@
void addFBits16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
}
void addFBits32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
}
void addFPImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addImm8s4Operands(MCInst &Inst, unsigned N) const {
@@ -1911,7 +1911,7 @@
// FIXME: We really want to scale the value here, but the LDRD/STRD
// instruction don't encode operands that way yet.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
}
void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
@@ -1919,7 +1919,7 @@
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
}
void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
@@ -1927,7 +1927,7 @@
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
+ Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
}
void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
@@ -1935,7 +1935,7 @@
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
}
void addImm1_16Operands(MCInst &Inst, unsigned N) const {
@@ -1943,7 +1943,7 @@
// The constant encodes as the immediate-1, and we store in the instruction
// the bits as encoded, so subtract off one here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
}
void addImm1_32Operands(MCInst &Inst, unsigned N) const {
@@ -1951,7 +1951,7 @@
// The constant encodes as the immediate-1, and we store in the instruction
// the bits as encoded, so subtract off one here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
}
void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
@@ -1960,7 +1960,7 @@
// zero.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Imm = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
+ Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
}
void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
@@ -1969,7 +1969,7 @@
// the instruction as well.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
+ Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
}
void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
@@ -1977,7 +1977,7 @@
// The operand is actually a t2_so_imm, but we have its bitwise
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(~CE->getValue()));
}
void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
@@ -1985,7 +1985,7 @@
// The operand is actually a t2_so_imm, but we have its
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(-CE->getValue()));
}
void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
@@ -1993,18 +1993,18 @@
// The operand is actually an imm0_4095, but we have its
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(-CE->getValue()));
}
void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
return;
}
const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
assert(SR && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateExpr(SR));
+ Inst.addOperand(MCOperand::createExpr(SR));
}
void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
@@ -2012,40 +2012,40 @@
if (isImm()) {
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (CE) {
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
return;
}
const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
assert(SR && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateExpr(SR));
+ Inst.addOperand(MCOperand::createExpr(SR));
return;
}
assert(isMem() && "Unknown value type!");
assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
+ Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
}
void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
}
void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
}
void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
}
void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
int32_t Imm = Memory.OffsetImm->getValue();
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
@@ -2055,19 +2055,19 @@
// If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup.
if (!isa<MCConstantExpr>(getImm())) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
return;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Memory.Alignment));
}
void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
@@ -2129,9 +2129,9 @@
Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
Memory.ShiftImm, Memory.ShiftType);
}
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
@@ -2144,8 +2144,8 @@
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
@@ -2154,9 +2154,9 @@
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
@@ -2172,9 +2172,9 @@
// here.
Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
}
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2182,8 +2182,8 @@
if (Kind == k_PostIndexRegister) {
int32_t Val =
ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
return;
}
@@ -2195,8 +2195,8 @@
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM3Opc(AddSub, Val);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
@@ -2205,8 +2205,8 @@
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
@@ -2217,8 +2217,8 @@
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM5Opc(AddSub, Val);
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2227,29 +2227,29 @@
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
// The lower two bits are always zero and as such are not encoded.
int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2265,14 +2265,14 @@
// If this is an immediate, it's a label reference.
if (isImm()) {
addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
// Otherwise, it's a normal memory reg+offset.
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2280,26 +2280,26 @@
// If this is an immediate, it's a label reference.
if (isImm()) {
addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
// Otherwise, it's a normal memory reg+offset.
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemTBBOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemTBHOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2307,50 +2307,50 @@
unsigned Val =
ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
Memory.ShiftImm, Memory.ShiftType);
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
}
void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
@@ -2361,7 +2361,7 @@
bool isAdd = Imm >= 0;
if (Imm == INT32_MIN) Imm = 0;
Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
@@ -2373,65 +2373,65 @@
if (Imm == INT32_MIN) Imm = 0;
// Immediate is scaled by 4.
Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
- Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
}
void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
// The sign, shift type, and shift amount are encoded in a single operand
// using the AM2 encoding helpers.
ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
PostIdxReg.ShiftTy);
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
}
void addBankedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
}
void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
}
void addVecListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
+ Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
}
void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
- Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
+ Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
+ Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
@@ -2439,7 +2439,7 @@
// The immediate encodes the type of constant as well as the value.
// Mask in that this is an i8 splat.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
}
void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
@@ -2448,7 +2448,7 @@
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi16splat(Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
@@ -2457,7 +2457,7 @@
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
@@ -2466,7 +2466,7 @@
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi32splat(Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
@@ -2475,7 +2475,7 @@
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi32splat(~Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
@@ -2489,7 +2489,7 @@
"always must be replaced with VMOVv8i8 or VMOVv16i8.");
unsigned B = ((~Value) & 0xff);
B |= 0xe00; // cmode = 0b1110
- Inst.addOperand(MCOperand::CreateImm(B));
+ Inst.addOperand(MCOperand::createImm(B));
}
void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -2502,7 +2502,7 @@
Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
else if (Value > 0xffffff)
Value = (Value >> 24) | 0x600;
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
@@ -2516,7 +2516,7 @@
"always must be replaced with VMOVv8i8 or VMOVv16i8.");
unsigned B = Value & 0xff;
B |= 0xe00; // cmode = 0b1110
- Inst.addOperand(MCOperand::CreateImm(B));
+ Inst.addOperand(MCOperand::createImm(B));
}
void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -2529,7 +2529,7 @@
Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
else if (Value > 0xffffff)
Value = (Value >> 24) | 0x600;
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
@@ -2541,7 +2541,7 @@
for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
Imm |= (Value & 1) << i;
}
- Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
+ Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
}
void print(raw_ostream &OS) const override;
@@ -6705,8 +6705,8 @@
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -6723,8 +6723,8 @@
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -6743,7 +6743,7 @@
// Immediate (mod_imm) will be in its encoded form, we must unencode it
// before passing it to the ADR instruction.
unsigned Enc = Inst.getOperand(2).getImm();
- TmpInst.addOperand(MCOperand::CreateImm(
+ TmpInst.addOperand(MCOperand::createImm(
ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
} else {
// Turn PC-relative expression into absolute expression.
@@ -6760,7 +6760,7 @@
getContext());
const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
getContext());
- TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
+ TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
}
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4));
@@ -6826,7 +6826,7 @@
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6850,9 +6850,9 @@
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6876,11 +6876,11 @@
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6900,7 +6900,7 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6922,9 +6922,9 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6946,11 +6946,11 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6972,13 +6972,13 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7018,7 +7018,7 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7040,9 +7040,9 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7064,11 +7064,11 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7110,14 +7110,14 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7137,18 +7137,18 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7168,22 +7168,22 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7204,7 +7204,7 @@
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7224,14 +7224,14 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7251,18 +7251,18 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7282,22 +7282,22 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7336,12 +7336,12 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7361,16 +7361,16 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7390,20 +7390,20 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7423,9 +7423,9 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7445,14 +7445,14 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7469,9 +7469,9 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7494,9 +7494,9 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7516,14 +7516,14 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7540,9 +7540,9 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7565,11 +7565,11 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7589,16 +7589,16 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7615,11 +7615,11 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7642,11 +7642,11 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7666,16 +7666,16 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7692,11 +7692,11 @@
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7721,9 +7721,9 @@
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7743,11 +7743,11 @@
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7769,9 +7769,9 @@
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(3)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -7792,11 +7792,11 @@
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7816,13 +7816,13 @@
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7844,11 +7844,11 @@
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(3)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -7912,14 +7912,14 @@
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
if (!isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
Inst = TmpInst;
return true;
@@ -7949,15 +7949,15 @@
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX)
- TmpInst.addOperand(MCOperand::CreateImm(Amount));
+ TmpInst.addOperand(MCOperand::createImm(Amount));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
Inst = TmpInst;
return true;
@@ -7981,7 +7981,7 @@
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out
@@ -8012,7 +8012,7 @@
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (Opc == ARM::MOVsi)
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out
@@ -8025,7 +8025,7 @@
TmpInst.setOpcode(ARM::MOVsi);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4)); // cc_out
@@ -8042,7 +8042,7 @@
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(4));
+ TmpInst.addOperand(MCOperand::createImm(4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8058,7 +8058,7 @@
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(-4));
+ TmpInst.addOperand(MCOperand::createImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8074,8 +8074,8 @@
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
- TmpInst.addOperand(MCOperand::CreateImm(4));
+ TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
+ TmpInst.addOperand(MCOperand::createImm(4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8092,7 +8092,7 @@
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
- TmpInst.addOperand(MCOperand::CreateImm(-4));
+ TmpInst.addOperand(MCOperand::createImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8105,7 +8105,7 @@
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2ADDri);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
break;
case ARM::t2SUBri12:
// If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
@@ -8114,7 +8114,7 @@
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2SUBri);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
break;
case ARM::tADDi8:
// If the immediate is in the range 0-7, we want tADDi3 iff Rd was
@@ -8187,7 +8187,7 @@
// same, we need to use the 32-bit encoding if it's available.
if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
Inst.setOpcode(ARM::t2ADDrr);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
return true;
}
break;
@@ -8240,7 +8240,7 @@
// the writeback tied operand.
if (hasWritebackToken)
Inst.insert(Inst.begin(),
- MCOperand::CreateReg(Inst.getOperand(0).getReg()));
+ MCOperand::createReg(Inst.getOperand(0).getReg()));
return true;
}
break;
@@ -8269,8 +8269,8 @@
assert (isThumbTwo());
Inst.setOpcode(ARM::t2LDMIA_UPD);
// Add the base register and writeback operands.
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
return true;
}
case ARM::tPUSH: {
@@ -8280,8 +8280,8 @@
assert (isThumbTwo());
Inst.setOpcode(ARM::t2STMDB_UPD);
// Add the base register and writeback operands.
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
return true;
}
case ARM::t2MOVi: {
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4c169a8..609fdb1 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -582,12 +582,12 @@
if (I == MI.end()) break;
if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && OpInfo[i-1].isPredicate()) continue;
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
}
// Most Thumb instructions don't have explicit predicates in the
@@ -646,22 +646,22 @@
for (unsigned i = 0; i < NumOps; ++i, ++I) {
if (I == MI.end()) break;
if (OpInfo[i].isPredicate()) {
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
}
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
@@ -894,7 +894,7 @@
return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -918,7 +918,7 @@
if (RegNo == 15)
{
- Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
+ Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success;
}
@@ -949,7 +949,7 @@
S = MCDisassembler::SoftFail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
- Inst.addOperand(MCOperand::CreateReg(RegisterPair));
+ Inst.addOperand(MCOperand::createReg(RegisterPair));
return S;
}
@@ -979,7 +979,7 @@
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1009,7 +1009,7 @@
return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1034,7 +1034,7 @@
return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1068,7 +1068,7 @@
RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1087,7 +1087,7 @@
return MCDisassembler::Fail;
unsigned Register = DPairDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1110,7 +1110,7 @@
return MCDisassembler::Fail;
unsigned Register = DPairSpacedDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1120,20 +1120,20 @@
// AL predicate is not allowed on Thumb1 branches.
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
if (Val == ARMCC::AL) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
} else
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val)
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
return MCDisassembler::Success;
}
@@ -1169,7 +1169,7 @@
Shift = ARM_AM::rrx;
unsigned Op = Shift | (imm << 3);
- Inst.addOperand(MCOperand::CreateImm(Op));
+ Inst.addOperand(MCOperand::createImm(Op));
return S;
}
@@ -1204,7 +1204,7 @@
break;
}
- Inst.addOperand(MCOperand::CreateImm(Shift));
+ Inst.addOperand(MCOperand::createImm(Shift));
return S;
}
@@ -1318,7 +1318,7 @@
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
uint32_t lsb_mask = (1U << lsb) - 1;
- Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
+ Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
return S;
}
@@ -1378,8 +1378,8 @@
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(coproc));
- Inst.addOperand(MCOperand::CreateImm(CRd));
+ Inst.addOperand(MCOperand::createImm(coproc));
+ Inst.addOperand(MCOperand::createImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1417,7 +1417,7 @@
case ARM::STC_PRE:
case ARM::STCL_PRE:
imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case ARM::t2LDC2_POST:
case ARM::t2LDC2L_POST:
@@ -1440,7 +1440,7 @@
default:
// The 'option' variant doesn't encode 'U' in the immediate since
// the immediate is unsigned [0,255].
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
}
@@ -1564,11 +1564,11 @@
Opc = ARM_AM::rrx;
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
} else {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(tmp));
+ Inst.addOperand(MCOperand::createImm(tmp));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1615,7 +1615,7 @@
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
else
shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
- Inst.addOperand(MCOperand::CreateImm(shift));
+ Inst.addOperand(MCOperand::createImm(shift));
return S;
}
@@ -1798,12 +1798,12 @@
return MCDisassembler::Fail;
if (type) {
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(U));
+ Inst.addOperand(MCOperand::createImm(U));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1834,7 +1834,7 @@
break;
}
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1936,7 +1936,7 @@
return MCDisassembler::Fail;
Inst.addOperand(
- MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
+ MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
return S;
}
@@ -1980,22 +1980,22 @@
if (imod && M) {
Inst.setOpcode(ARM::CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
S = MCDisassembler::SoftFail;
}
@@ -2020,17 +2020,17 @@
if (imod && M) {
Inst.setOpcode(ARM::t2CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::t2CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::t2CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> this is a HINT instruction
@@ -2038,7 +2038,7 @@
// HINT are defined only for immediate in [0..4]
if(imm > 4) return MCDisassembler::Fail;
Inst.setOpcode(ARM::t2HINT);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return S;
@@ -2063,7 +2063,7 @@
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -2087,7 +2087,7 @@
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2166,7 +2166,7 @@
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return S;
}
@@ -2184,7 +2184,7 @@
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (Rn == 15)
tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
@@ -2203,9 +2203,9 @@
return MCDisassembler::Fail;
if (U)
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
else
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
return S;
}
@@ -2237,7 +2237,7 @@
int imm32 = SignExtend32<25>(tmp << 1);
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return Status;
}
@@ -2255,13 +2255,13 @@
imm |= fieldFromInstruction(Insn, 24, 1) << 1;
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
return S;
}
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2279,9 +2279,9 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!align)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else
- Inst.addOperand(MCOperand::CreateImm(4 << align));
+ Inst.addOperand(MCOperand::createImm(4 << align));
return S;
}
@@ -2475,7 +2475,7 @@
case ARM::VLD2b8wb_register:
case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_register:
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
@@ -2510,7 +2510,7 @@
//
// The fixed offset encodes as Rm == 0xd, so we check for that.
if (Rm == 0xd) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
break;
}
// Fall through to handle the register offset variant.
@@ -2676,7 +2676,7 @@
case ARM::VST2b32wb_register:
if (Rm == 0xF)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD:
@@ -2705,7 +2705,7 @@
switch (Inst.getOpcode()) {
default:
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2917,7 +2917,7 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post-
@@ -2963,11 +2963,11 @@
}
if (Rm != 0xF)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
@@ -3000,10 +3000,10 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3052,10 +3052,10 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3086,7 +3086,7 @@
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
case ARM::VORRiv4i16:
@@ -3124,32 +3124,32 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(8 << size));
+ Inst.addOperand(MCOperand::createImm(8 << size));
return S;
}
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(8 - Val));
+ Inst.addOperand(MCOperand::createImm(8 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(16 - Val));
+ Inst.addOperand(MCOperand::createImm(16 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(32 - Val));
+ Inst.addOperand(MCOperand::createImm(32 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Val));
+ Inst.addOperand(MCOperand::createImm(64 - Val));
return MCDisassembler::Success;
}
@@ -3205,11 +3205,11 @@
case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi:
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
break;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3217,7 +3217,7 @@
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
return MCDisassembler::Success;
}
@@ -3225,7 +3225,7 @@
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
return MCDisassembler::Success;
}
@@ -3233,7 +3233,7 @@
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(Val << 1));
+ Inst.addOperand(MCOperand::createImm(Val << 1));
return MCDisassembler::Success;
}
@@ -3261,7 +3261,7 @@
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3270,7 +3270,7 @@
uint64_t Address, const void *Decoder) {
unsigned imm = Val << 2;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
return MCDisassembler::Success;
@@ -3278,8 +3278,8 @@
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -3307,7 +3307,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3641,7 +3641,7 @@
else
imm = -imm;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3649,12 +3649,12 @@
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
- Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
+ Inst.addOperand(MCOperand::createImm(INT32_MIN));
else {
int imm = Val & 0xFF;
if (!(Val & 0x100)) imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm * 4));
+ Inst.addOperand(MCOperand::createImm(imm * 4));
}
return MCDisassembler::Success;
@@ -3685,7 +3685,7 @@
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3697,7 +3697,7 @@
imm = INT32_MIN;
else if (!(Val & 0x100))
imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3830,7 +3830,7 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3840,9 +3840,9 @@
uint64_t Address, const void *Decoder) {
unsigned imm = fieldFromInstruction(Insn, 0, 7);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3857,14 +3857,14 @@
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
@@ -3877,8 +3877,8 @@
unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
unsigned flags = fieldFromInstruction(Insn, 0, 3);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(flags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(flags));
return MCDisassembler::Success;
}
@@ -3891,7 +3891,7 @@
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(add));
+ Inst.addOperand(MCOperand::createImm(add));
return S;
}
@@ -3916,7 +3916,7 @@
if (!tryAddingSymbolicOperand(Address,
(Address & ~2u) + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -3930,7 +3930,7 @@
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4001,16 +4001,16 @@
unsigned imm = fieldFromInstruction(Val, 0, 8);
switch (byte) {
case 0:
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case 1:
- Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
+ Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
break;
case 2:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
break;
case 3:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
(imm << 8) | imm));
break;
}
@@ -4018,7 +4018,7 @@
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
unsigned rot = fieldFromInstruction(Val, 7, 5);
unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return MCDisassembler::Success;
@@ -4029,7 +4029,7 @@
uint64_t Address, const void *Decoder){
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
return MCDisassembler::Success;
}
@@ -4052,7 +4052,7 @@
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -4061,7 +4061,7 @@
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4070,7 +4070,7 @@
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4132,7 +4132,7 @@
if (Val == 0)
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -4155,7 +4155,7 @@
return MCDisassembler::SoftFail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4359,18 +4359,18 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4424,18 +4424,18 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4490,20 +4490,20 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4553,20 +4553,20 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4622,13 +4622,13 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4637,7 +4637,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4685,13 +4685,13 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4700,7 +4700,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4765,13 +4765,13 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4782,7 +4782,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4837,13 +4837,13 @@
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4854,7 +4854,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4925,8 +4925,8 @@
if (mask == 0x0)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(pred));
- Inst.addOperand(MCOperand::CreateImm(mask));
+ Inst.addOperand(MCOperand::createImm(pred));
+ Inst.addOperand(MCOperand::createImm(mask));
return S;
}
@@ -5012,7 +5012,7 @@
Val |= fieldFromInstruction(Insn, 12, 3) << 8;
Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Val |= sign1 << 12;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
return MCDisassembler::Success;
}
@@ -5024,7 +5024,7 @@
// Shift of "asr #32" is not allowed in Thumb2 mode.
if (Val == 0x20) S = MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -5080,7 +5080,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5110,7 +5110,7 @@
return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5159,13 +5159,13 @@
if (Rt == Rt2)
S = MCDisassembler::SoftFail;
- Inst.addOperand(MCOperand::CreateImm(cop));
- Inst.addOperand(MCOperand::CreateImm(opc1));
+ Inst.addOperand(MCOperand::createImm(cop));
+ Inst.addOperand(MCOperand::createImm(opc1));
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(CRm));
+ Inst.addOperand(MCOperand::createImm(CRm));
return S;
}
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 1c5a795..d826afd 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -284,7 +284,7 @@
if (isStore)
NewMI.addOperand(MI->getOperand(0));
- NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(
+ NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
NewMI.addOperand(NewReg);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 590d72f..7ff15ca 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -238,9 +238,9 @@
if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
RelaxedOp == ARM::tHINT) {
Res.setOpcode(RelaxedOp);
- Res.addOperand(MCOperand::CreateImm(0));
- Res.addOperand(MCOperand::CreateImm(14));
- Res.addOperand(MCOperand::CreateReg(0));
+ Res.addOperand(MCOperand::createImm(0));
+ Res.addOperand(MCOperand::createImm(14));
+ Res.addOperand(MCOperand::createReg(0));
return;
}
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 29aaa15..028119c 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -27,10 +27,10 @@
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tMOVr);
- NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
- NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R8));
+ NopInst.addOperand(MCOperand::createReg(ARM::R8));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
}
unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 829aa7a..dc74f4e 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -35,9 +35,9 @@
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tHINT);
- NopInst.addOperand(MCOperand::CreateImm(0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createImm(0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
}
unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {