commit e96f804ebae72e2013756aacb8bfa1bb7cb204c3
author Anshuman Dasgupta <adasgupt@codeaurora.org> Wed Feb 13 22:56:34 2013 +0000
committer Anshuman Dasgupta <adasgupt@codeaurora.org> Wed Feb 13 22:56:34 2013 +0000
tree d7c2485fe7647617e68f6913e29b3bae18d0054c
parent a66c4d96f02a07f2956a3f029e216a8967463f5d

Hexagon: add support for predicate-GPR copies.

llvm-svn: 175102

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 6801467..d30cdda 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -426,6 +426,18 @@
     BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
     return;
   }
+  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
+      Hexagon::IntRegsRegClass.contains(DestReg)) {
+    BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
+      addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
+      Hexagon::PredRegsRegClass.contains(DestReg)) {
+    BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
+      addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
 
   llvm_unreachable("Unimplemented");
 }