Add some new instructions. Fix the asm string for sbb32rr
llvm-svn: 16759
diff --git a/llvm/lib/Target/X86/X86PeepholeOpt.cpp b/llvm/lib/Target/X86/X86PeepholeOpt.cpp
index f03e339..d041480 100644
--- a/llvm/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/llvm/lib/Target/X86/X86PeepholeOpt.cpp
@@ -124,7 +124,8 @@
#endif
case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
- case X86::SUB16ri: case X86::SUB32ri: case X86::SBB32ri:
+ case X86::SUB16ri: case X86::SUB32ri:
+ case X86::SBB16ri: case X86::SBB32ri:
case X86::AND16ri: case X86::AND32ri:
case X86::OR16ri: case X86::OR32ri:
case X86::XOR16ri: case X86::XOR32ri:
@@ -141,6 +142,7 @@
case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
+ case X86::SBB16ri: Opcode = X86::SBB16ri8; break;
case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
case X86::AND16ri: Opcode = X86::AND16ri8; break;
case X86::AND32ri: Opcode = X86::AND32ri8; break;
@@ -159,7 +161,8 @@
return false;
case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
- case X86::SUB16mi: case X86::SUB32mi: case X86::SBB32mi:
+ case X86::SUB16mi: case X86::SUB32mi:
+ case X86::SBB16mi: case X86::SBB32mi:
case X86::AND16mi: case X86::AND32mi:
case X86::OR16mi: case X86::OR32mi:
case X86::XOR16mi: case X86::XOR32mi:
@@ -176,6 +179,7 @@
case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
+ case X86::SBB16mi: Opcode = X86::SBB16mi8; break;
case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
case X86::AND16mi: Opcode = X86::AND16mi8; break;
case X86::AND32mi: Opcode = X86::AND32mi8; break;