commit ea4359e9228b34156cd453946473bcd581c581f3
author Matthias Braun <matze@braunis.de> Thu Jan 11 22:30:43 2018 +0000
committer Matthias Braun <matze@braunis.de> Thu Jan 11 22:30:43 2018 +0000
tree daa098b3dea30a27b6489a64f00b47e8d2b8264a
parent cbca487f4931ff089feebaa7d356886baa510847

PeepholeOptimizer: Fix for vregs without defs

The PeepholeOptimizer would fail for vregs without a definition. If this
was caused by an undef operand abort to keep the code simple (so we
don't need to add logic everywhere to replicate the undef flag).

Differential Revision: https://reviews.llvm.org/D40763

llvm-svn: 322319

llvm/lib/CodeGen/PeepholeOptimizer.cpp

diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 11acbe6..1090550 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1882,6 +1882,8 @@
     return ValueTrackerResult();
   // Otherwise, we want the whole source.
   const MachineOperand &Src = Def->getOperand(1);
+  if (Src.isUndef())
+    return ValueTrackerResult();
   return ValueTrackerResult(Src.getReg(), Src.getSubReg());
 }
 
@@ -1925,6 +1927,8 @@
   }
 
   const MachineOperand &Src = Def->getOperand(SrcIdx);
+  if (Src.isUndef())
+    return ValueTrackerResult();
   return ValueTrackerResult(Src.getReg(), Src.getSubReg());
 }
 
@@ -2093,6 +2097,10 @@
   for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
     auto &MO = Def->getOperand(i);
     assert(MO.isReg() && "Invalid PHI instruction");
+    // We have no code to deal with undef operands. They shouldn't happen in
+    // normal programs anyway.
+    if (MO.isUndef())
+      return ValueTrackerResult();
     Res.addSource(MO.getReg(), MO.getSubReg());
   }
 
@@ -2149,9 +2157,14 @@
     // If we can still move up in the use-def chain, move to the next
     // definition.
     if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
-      Def = MRI.getVRegDef(Reg);
-      DefIdx = MRI.def_begin(Reg).getOperandNo();
-      DefSubReg = Res.getSrcSubReg(0);
+      MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
+      if (DI != MRI.def_end()) {
+        Def = DI->getParent();
+        DefIdx = DI.getOperandNo();
+        DefSubReg = Res.getSrcSubReg(0);
+      } else {
+        Def = nullptr;
+      }
       return Res;
     }
   }