Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792.
llvm-svn: 371809
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 7d48634..ad19741 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -74,7 +74,7 @@
.addReg(SrcReg)
.addImm(Val)
.setMIFlag(Flag);
- } else {
+ } else if (isInt<32>(Val)) {
unsigned Opc = RISCV::ADD;
bool isSub = Val < 0;
if (isSub) {
@@ -83,11 +83,13 @@
}
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
+ TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
.addReg(SrcReg)
.addReg(ScratchReg, RegState::Kill)
.setMIFlag(Flag);
+ } else {
+ report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 759fdab..46ace19 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -14,7 +14,6 @@
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
-#include "Utils/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -157,42 +156,24 @@
BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
}
-void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag) const {
- MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
- Register SrcReg = RISCV::X0;
- Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- unsigned Num = 0;
+void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DstReg, uint64_t Val,
+ MachineInstr::MIFlag Flag) const {
+ assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
- if (!IsRV64 && !isInt<32>(Val))
- report_fatal_error("Should only materialize 32-bit constants for RV32");
+ // TODO: If the value can be materialized using only one instruction, only
+ // insert a single instruction.
- RISCVMatInt::InstSeq Seq;
- RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
- assert(Seq.size() > 0);
-
- for (RISCVMatInt::Inst &Inst : Seq) {
- // Write the final result to DstReg if it's the last instruction in the Seq.
- // Otherwise, write the result to the temp register.
- if (++Num == Seq.size())
- Result = DstReg;
-
- if (Inst.Opc == RISCV::LUI) {
- BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
- .addImm(Inst.Imm)
- .setMIFlag(Flag);
- } else {
- BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
- .addReg(SrcReg, RegState::Kill)
- .addImm(Inst.Imm)
- .setMIFlag(Flag);
- }
- // Only the first instruction has X0 as its source.
- SrcReg = Result;
- }
+ uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
+ uint64_t Lo12 = SignExtend64<12>(Val);
+ BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
+ .addImm(Hi20)
+ .setMIFlag(Flag);
+ BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+ .addReg(DstReg, RegState::Kill)
+ .addImm(Lo12)
+ .setMIFlag(Flag);
}
// The contents of values added to Cond are not examined outside of
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index fa930dd..141fe30 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -46,10 +46,10 @@
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
- // Materializes the given integer Val into DstReg.
- void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
+ // Materializes the given int32 Val into DstReg.
+ void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DstReg, uint64_t Val,
+ MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index aa6d06d..2bbce25 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -110,7 +110,7 @@
// The offset won't fit in an immediate, so use a scratch register instead
// Modify Offset and FrameReg appropriately
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm(MBB, II, DL, ScratchReg, Offset);
+ TII->movImm32(MBB, II, DL, ScratchReg, Offset);
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
.addReg(FrameReg)
.addReg(ScratchReg, RegState::Kill);