commit ea7bb570580d1a82c8654d0ee3ce6b0a4419a35b
author Amaury de la Vieuville <amaury.dlv@gmail.com> Sat Jun 08 13:29:11 2013 +0000
committer Amaury de la Vieuville <amaury.dlv@gmail.com> Sat Jun 08 13:29:11 2013 +0000
tree bb04066dca83e7315258553231e90884204794bb
parent 855b17d1bc24b3bab648b48bbb6e304af2884c36

ARM: fix VCVT decoding

UNPRED was reported instead of UNDEF

llvm-svn: 183608

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 824ffbf..0b93f91 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4441,7 +4441,7 @@
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
 
-  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+  if (!(imm & 0x20)) return MCDisassembler::Fail;
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;
@@ -4469,7 +4469,7 @@
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
 
-  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+  if (!(imm & 0x20)) return MCDisassembler::Fail;
 
   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;