| commit | ea973bda26d4b04b1bf6700401c7eb77b1873820 | [log] [tgz] |
|---|---|---|
| author | Nadav Rotem <nrotem@apple.com> | Thu Aug 30 19:17:29 2012 +0000 |
| committer | Nadav Rotem <nrotem@apple.com> | Thu Aug 30 19:17:29 2012 +0000 |
| tree | e5025a0df7f81c8392b06c996dd62bc3e2dbf4a2 | |
| parent | aad745a024a3d0fd573ac9649d4c659e6a713702 [diff] |
Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926