Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
llvm-svn: 183493
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index d07a595..928a43d 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -177,7 +177,7 @@
class Filler : public MachineFunctionPass {
public:
Filler(TargetMachine &tm)
- : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
+ : MachineFunctionPass(ID), TM(tm) { }
virtual const char *getPassName() const {
return "Mips Delay Slot Filler";
@@ -243,7 +243,6 @@
bool terminateSearch(const MachineInstr &Candidate) const;
TargetMachine &TM;
- const TargetInstrInfo *TII;
static char ID;
};
@@ -514,6 +513,8 @@
}
// Bundle the NOP to the instruction with the delay slot.
+ const MipsInstrInfo *TII =
+ static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
}