commit eb05c610b487f74e9d4f64ba999807b76c9289f1
author Tom Stellard <thomas.stellard@amd.com> Thu Feb 26 17:08:43 2015 +0000
committer Tom Stellard <thomas.stellard@amd.com> Thu Feb 26 17:08:43 2015 +0000
tree 52dfdd48c10889aed4be59c82ef0a476908b95a5
parent 6e09bca0ef1961d0b2eb24395420349054a52ce0

R600/SI: Remove M0 from DS assembly strings

This matches the assembly syntax for the proprietary compiler.

llvm-svn: 230645

llvm/lib/Target/R600/SIInstrInfo.td

diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index 9f5d3e8..e2747dc 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -1523,7 +1523,7 @@
   asm,
   (outs regClass:$vdst),
   (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
-  asm#" $vdst, $addr"#"$offset"#" [M0]",
+  asm#" $vdst, $addr"#"$offset",
   []>;
 
 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
@@ -1545,7 +1545,7 @@
   (outs regClass:$vdst),
   (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
         M0Reg:$m0),
-  asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
+  asm#" $vdst, $addr"#"$offset0"#"$offset1",
   []>;
 
 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
@@ -1566,7 +1566,7 @@
   asm,
   (outs),
   (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
-  asm#" $addr, $data0"#"$offset"#" [M0]",
+  asm#" $addr, $data0"#"$offset",
   []>;
 
 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
@@ -1588,7 +1588,7 @@
   (outs),
   (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
        ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
-  asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
+  asm#" $addr, $data0, $data1"#"$offset0"#"$offset1",
   []>;
 
 // 1 address, 1 data.
@@ -1612,7 +1612,7 @@
   op, asm,
   (outs rc:$vdst),
   (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
-  asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
+  asm#" $vdst, $addr, $data0"#"$offset", [], noRetOp>;
 
 // 1 address, 2 data.
 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
@@ -1633,7 +1633,7 @@
   op, asm,
   (outs rc:$vdst),
   (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
-  asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
+  asm#" $vdst, $addr, $data0, $data1"#"$offset",
   [], noRetOp>;
 
 // 1 address, 2 data.
@@ -1655,7 +1655,7 @@
   op, asm,
   (outs),
   (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
-  asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
+  asm#" $addr, $data0, $data1"#"$offset",
   [], noRetOp>;
 
 // 1 address, 1 data.
@@ -1677,7 +1677,7 @@
   op, asm,
   (outs),
   (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
-  asm#" $addr, $data0"#"$offset"#" [M0]",
+  asm#" $addr, $data0"#"$offset",
   [], noRetOp>;
 
 //===----------------------------------------------------------------------===//