[WebAssembly] Add simd128-unimplemented subtarget feature
This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renamed simd128-unimplemented, since naming it
unimplemented-simd128 somehow made the simd128 feature flag enable the
unimplemented-simd128 feature on Windows.
llvm-svn: 350791
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td
index ec9dbff..243a71f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.td
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -25,6 +25,13 @@
def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
"Enable 128-bit SIMD">;
+
+def FeatureSIMD128Unimplemented :
+ SubtargetFeature<"simd128-unimplemented",
+ "HasSIMD128Unimplemented", "true",
+ "Enable 128-bit SIMD not yet implemented in engines",
+ [FeatureSIMD128]>;
+
def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
"Enable Atomics">;
def FeatureNontrappingFPToInt :
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index a452a00..f687c4d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -44,8 +44,6 @@
#define DEBUG_TYPE "wasm-fastisel"
-extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
-
namespace {
class WebAssemblyFastISel final : public FastISel {
@@ -145,7 +143,7 @@
break;
case MVT::v2i64:
case MVT::v2f64:
- if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs)
+ if (Subtarget->hasSIMD128Unimplemented())
return VT;
break;
default:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
index 29678f3..0a7464c 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -25,8 +25,6 @@
#define DEBUG_TYPE "wasm-isel"
-extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
-
//===--------------------------------------------------------------------===//
/// WebAssembly-specific code to select WebAssembly machine instructions for
/// SelectionDAG operations.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index d267358..1f33888 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -37,12 +37,6 @@
#define DEBUG_TYPE "wasm-lower"
-// Emit proposed instructions that may not have been implemented in engines
-cl::opt<bool> EnableUnimplementedWasmSIMDInstrs(
- "wasm-enable-unimplemented-simd",
- cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"),
- cl::init(false));
-
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
@@ -70,7 +64,7 @@
addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
- if (EnableUnimplementedWasmSIMDInstrs) {
+ if (Subtarget->hasSIMD128Unimplemented()) {
addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
}
@@ -135,7 +129,7 @@
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) {
setOperationAction(Op, T, Expand);
}
- if (EnableUnimplementedWasmSIMDInstrs) {
+ if (Subtarget->hasSIMD128Unimplemented()) {
setOperationAction(Op, MVT::v2i64, Expand);
}
}
@@ -149,7 +143,7 @@
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {
setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
}
- if (EnableUnimplementedWasmSIMDInstrs) {
+ if (Subtarget->hasSIMD128Unimplemented()) {
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
}
@@ -160,7 +154,7 @@
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
setOperationAction(Op, T, Custom);
- if (EnableUnimplementedWasmSIMDInstrs)
+ if (Subtarget->hasSIMD128Unimplemented())
for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
setOperationAction(Op, MVT::v2i64, Custom);
}
@@ -170,7 +164,7 @@
for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
setOperationAction(Op, T, Expand);
- if (EnableUnimplementedWasmSIMDInstrs)
+ if (Subtarget->hasSIMD128Unimplemented())
for (auto T : {MVT::v2i64, MVT::v2f64})
setOperationAction(Op, T, Expand);
}
@@ -179,8 +173,10 @@
// sign-extend from.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (!Subtarget->hasSignExt()) {
+ // Sign extends are legal only when extending a vector extract
+ auto Action = Subtarget->hasSIMD128() ? Custom : Expand;
for (auto T : {MVT::i8, MVT::i16, MVT::i32})
- setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action);
}
for (auto T : MVT::integer_vector_valuetypes())
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
@@ -225,7 +221,7 @@
}
// Expand additional SIMD ops that V8 hasn't implemented yet
- if (Subtarget->hasSIMD128() && !EnableUnimplementedWasmSIMDInstrs) {
+ if (Subtarget->hasSIMD128() && !Subtarget->hasSIMD128Unimplemented()) {
setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
}
@@ -236,7 +232,7 @@
setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
}
- if (EnableUnimplementedWasmSIMDInstrs) {
+ if (Subtarget->hasSIMD128Unimplemented()) {
for (auto T : {MVT::v2i64, MVT::v2f64}) {
setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
@@ -900,6 +896,8 @@
return LowerAccessVectorElement(Op, DAG);
case ISD::INTRINSIC_VOID:
return LowerINTRINSIC_VOID(Op, DAG);
+ case ISD::SIGN_EXTEND_INREG:
+ return LowerSIGN_EXTEND_INREG(Op, DAG);
case ISD::VECTOR_SHUFFLE:
return LowerVECTOR_SHUFFLE(Op, DAG);
case ISD::SHL:
@@ -1102,6 +1100,22 @@
}
SDValue
+WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
+ SelectionDAG &DAG) const {
+ // If sign extension operations are disabled, allow sext_inreg only if operand
+ // is a vector extract. SIMD does not depend on sign extension operations, but
+ // allowing sext_inreg in this context lets us have simple patterns to select
+ // extract_lane_s instructions. Expanding sext_inreg everywhere would be
+ // simpler in this file, but would necessitate large and brittle patterns to
+ // undo the expansion and select extract_lane_s instructions.
+ assert(!Subtarget->hasSignExt() && Subtarget->hasSIMD128());
+ if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT)
+ return Op;
+ // Otherwise expand
+ return SDValue();
+}
+
+SDValue
WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
index 8007681..59f4230 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
@@ -99,6 +99,7 @@
SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
index d172537..14e2de0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
@@ -20,7 +20,9 @@
def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
AssemblerPredicate<"FeatureSIMD128", "simd128">;
-def HasUnimplementedSIMD : Predicate<"EnableUnimplementedWasmSIMDInstrs">;
+def HasUnimplementedSIMD :
+ Predicate<"Subtarget->hasSIMD128Unimplemented()">,
+ AssemblerPredicate<"FeatureSIMD128Unimplemented", "simd128-unimplemented">;
def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
AssemblerPredicate<"FeatureAtomics", "atomics">;
def HasNontrappingFPToInt :
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
index b170dbf..bd2e995 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
@@ -30,6 +30,7 @@
class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
bool HasSIMD128;
+ bool HasSIMD128Unimplemented;
bool HasAtomics;
bool HasNontrappingFPToInt;
bool HasSignExt;
@@ -78,6 +79,7 @@
// Predicates used by WebAssemblyInstrInfo.td.
bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
bool hasSIMD128() const { return HasSIMD128; }
+ bool hasSIMD128Unimplemented() const { return HasSIMD128Unimplemented; }
bool hasAtomics() const { return HasAtomics; }
bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
bool hasSignExt() const { return HasSignExt; }