commit ecd0b83312bbed70380a0337a480b1cf698a0f6b
author Francis Visoiu Mistrih <francisvm@yahoo.com> Tue Jan 16 10:53:11 2018 +0000
committer Francis Visoiu Mistrih <francisvm@yahoo.com> Tue Jan 16 10:53:11 2018 +0000
tree af4df4289d8482bbab5283fa22573961d0ad7a29
parent 45ef5036c929b73e180d0c959c05b1a6bda07162

[CodeGen][NFC] Correct case for printSubRegIdx

llvm-svn: 322541

llvm/lib/CodeGen/MIRPrinter.cpp

diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 90515a6..5e7a258 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -744,7 +744,7 @@
   case MachineOperand::MO_Immediate:
     if (MI.isOperandSubregIdx(OpIdx)) {
       MachineOperand::printTargetFlags(OS, Op);
-      MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
+      MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
       break;
     }
     LLVM_FALLTHROUGH;

llvm/lib/CodeGen/MachineInstr.cpp

diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index eba100e..47974a2 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1397,7 +1397,7 @@
       LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
       unsigned TiedOperandIdx = getTiedOperandIdx(i);
       if (MO.isImm() && isOperandSubregIdx(i))
-        MachineOperand::printSubregIdx(OS, MO.getImm(), TRI);
+        MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
       else
         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);

llvm/lib/CodeGen/MachineOperand.cpp

diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index b4bfa3f..9d0c93e 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -440,7 +440,7 @@
     OS << "<unknown>";
 }
 
-void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
+void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
                                     const TargetRegisterInfo *TRI) {
   OS << "%subreg.";
   if (TRI)