diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 88c6ad0..f111d87 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -27,7 +27,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/VectorExtras.h"
@@ -347,7 +346,7 @@
   NeededGPRs = 0;
   StackPad = 0;
   GPRPad = 0;
-  unsigned align = (Flags >> SDISelParamFlags::OrigAlignmentOffs);
+  unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
   GPRPad = NumGPRs % ((align + 3)/4);
   StackPad = StackOffset % align;
   unsigned firstGPR = NumGPRs + GPRPad;
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
index 1e7c79f..e8ae5a3 100644
--- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -337,10 +337,12 @@
     case MVT::i32:
       // Promote the integer to 64 bits.  If the input type is signed use a
       // sign extend, otherwise use a zero extend.
-      if (Args[i].isSigned)
+      if (Args[i].isSExt)
         Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
-      else
+      else if (Args[i].isZExt)
         Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
+      else
+        Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
       break;
     case MVT::i64:
     case MVT::f64:
diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
index 1c7c51d..4bd7cba 100644
--- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
@@ -341,9 +341,11 @@
       case MVT::i32: {
         //promote to 64-bits, sign/zero extending based on type
         //of the argument
-        ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-        if (Args[i].isSigned)
+        ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+        if (Args[i].isSExt)
           ExtendKind = ISD::SIGN_EXTEND;
+        else if (Args[i].isZExt)
+          ExtendKind = ISD::ZERO_EXTEND;
         Val = DAG.getNode(ExtendKind, MVT::i64, Val);
         // XXX: fall through
       }
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 647007e..7275ce6 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -516,9 +516,11 @@
     case MVT::i16: {
       // Promote the integer to 32-bits.  If the input type is signed, use a
       // sign extend, otherwise use a zero extend.
-      ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-      if (Args[i].isSigned)
+      ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+      if (Args[i].isSExt)
         ExtendKind = ISD::SIGN_EXTEND;
+      else if (Args[i].isZExt)
+        ExtendKind = ISD::ZERO_EXTEND;
       Val = DAG.getNode(ExtendKind, MVT::i32, Val);
       // FALL THROUGH
     }
diff --git a/llvm/lib/Target/TargetCallingConv.td b/llvm/lib/Target/TargetCallingConv.td
index 3f71a1d..b91627e 100644
--- a/llvm/lib/Target/TargetCallingConv.td
+++ b/llvm/lib/Target/TargetCallingConv.td
@@ -38,7 +38,7 @@
 
 /// CCIfInReg - If this argument is marked with the 'inreg' attribute, apply
 /// the specified action.
-class CCIfInReg<CCAction A> : CCIf<"ArgFlags & SDISelParamFlags::InReg", A> {}
+class CCIfInReg<CCAction A> : CCIf<"ArgFlags & ISD::ParamFlags::InReg", A> {}
 
 
 /// CCAssignToReg - This action matches if there is a register in the specified
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9bcff7a..1d2c623 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29,7 +29,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetOptions.h"
@@ -677,7 +676,7 @@
     // If this is an sret function, the return should pop the hidden pointer.
     if (NumArgs &&
         (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
-         SDISelParamFlags::StructReturn))
+         ISD::ParamFlags::StructReturn))
       BytesToPopOnReturn = 4;  
     
     BytesCallerReserves = StackSize;
@@ -751,7 +750,7 @@
   // If the first argument is an sret pointer, remember it.
   bool isSRet = NumOps &&
     (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
-     SDISelParamFlags::StructReturn);
+     ISD::ParamFlags::StructReturn);
   
   if (!MemOpChains.empty())
     Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
@@ -3408,16 +3407,10 @@
     TargetLowering::ArgListEntry Entry;
     Entry.Node = Op.getOperand(1);
     Entry.Ty = IntPtrTy;
-    Entry.isSigned = false;
-    Entry.isInReg = false;
-    Entry.isSRet = false;
     Args.push_back(Entry);
     // Extend the unsigned i8 argument to be an int value for the call.
     Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
     Entry.Ty = IntPtrTy;
-    Entry.isSigned = false;
-    Entry.isInReg = false;
-    Entry.isSRet = false;
     Args.push_back(Entry);
     Entry.Node = Op.getOperand(3);
     Args.push_back(Entry);
@@ -3568,9 +3561,6 @@
     TargetLowering::ArgListTy Args;
     TargetLowering::ArgListEntry Entry;
     Entry.Ty = getTargetData()->getIntPtrType();
-    Entry.isSigned = false;
-    Entry.isInReg = false;
-    Entry.isSRet = false;
     Entry.Node = Op.getOperand(1); Args.push_back(Entry);
     Entry.Node = Op.getOperand(2); Args.push_back(Entry);
     Entry.Node = Op.getOperand(3); Args.push_back(Entry);