[RISCV] Implement MC layer support for the fence.tso instruction
The instruction makes use of a previously ignored field in the fence
instruction. It is introduced in the version 2.3 draft of the RISC-V
specification after much work by the Memory Model Task Group.
As clarified here <https://github.com/riscv/riscv-isa-manual/issues/186>,
the fence.tso assembler mnemonic does not have operands.
llvm-svn: 334278
diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s
index 5171b5e..4491bd8 100644
--- a/llvm/test/MC/RISCV/rv32i-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-valid.s
@@ -205,6 +205,9 @@
# CHECK-INST: fence w, ir
# CHECK: encoding: [0x0f,0x00,0xa0,0x01]
fence w,ir
+# CHECK-INST: fence.tso
+# CHECK: encoding: [0x0f,0x00,0x30,0x83]
+fence.tso
# CHECK-INST: fence.i
# CHECK: encoding: [0x0f,0x10,0x00,0x00]