commit ed78aaf093280af5686e0eda82a12ca24eb72baa
author John Brawn <john.brawn@arm.com> Thu Jun 22 10:30:53 2017 +0000
committer John Brawn <john.brawn@arm.com> Thu Jun 22 10:30:53 2017 +0000
tree 3aebeeacbc08855a1607c8b5ff5c0119c5d95289
parent 192f74a84d4b514372de166e3d3e72d2788a2ae0

[ARM] Add .w aliases of MOV with shifted operand

These appear to have been simply missing.

Differential Revision: https://reviews.llvm.org/D34461

llvm-svn: 305993

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 51e01184..891b5c6 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8160,7 +8160,8 @@
         isARMLowRegister(Inst.getOperand(1).getReg()) &&
         isARMLowRegister(Inst.getOperand(2).getReg()) &&
         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
-        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
+        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
+        !HasWideQualifier)
       isNarrow = true;
     MCInst TmpInst;
     unsigned newOpc;
@@ -8194,7 +8195,8 @@
     bool isNarrow = false;
     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
         isARMLowRegister(Inst.getOperand(1).getReg()) &&
-        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
+        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
+        !HasWideQualifier)
       isNarrow = true;
     MCInst TmpInst;
     unsigned newOpc;