[ARM][AArch64] Add CSDB speculation barrier instruction
This adds the CSDB instruction, which is a new barrier instruction
described by the whitepaper at [1].
This is in encoding space which was previously executed as a NOP, so it is
available for all targets that have the relevant NOP encoding space. This
matches the binutils behaviour for these instructions [2][3].
[1] https://developer.arm.com/support/security-update
[2] https://sourceware.org/ml/binutils/2018-01/msg00116.html
[3] https://sourceware.org/ml/binutils/2018-01/msg00120.html
llvm-svn: 324324
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 55a73ff..3d25188 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6616,19 +6616,22 @@
break;
}
case ARM::HINT:
- case ARM::t2HINT:
- if (hasRAS()) {
- // ESB is not predicable (pred must be AL)
- unsigned Imm8 = Inst.getOperand(0).getImm();
- unsigned Pred = Inst.getOperand(1).getImm();
- if (Imm8 == 0x10 && Pred != ARMCC::AL)
- return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
- "predicable, but condition "
- "code specified");
- }
- // Without the RAS extension, this behaves as any other unallocated hint.
+ case ARM::t2HINT: {
+ unsigned Imm8 = Inst.getOperand(0).getImm();
+ unsigned Pred = Inst.getOperand(1).getImm();
+ // ESB is not predicable (pred must be AL). Without the RAS extension, this
+ // behaves as any other unallocated hint.
+ if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
+ return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
+ "predicable, but condition "
+ "code specified");
+ if (Imm8 == 0x14 && Pred != ARMCC::AL)
+ return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
+ "predicable, but condition "
+ "code specified");
break;
}
+ }
return false;
}