TableGen: use PrintMethods to print more aliases
llvm-svn: 208607
diff --git a/llvm/test/CodeGen/ARM64/atomic-128.ll b/llvm/test/CodeGen/ARM64/atomic-128.ll
index 925a4b0..3b43aa1 100644
--- a/llvm/test/CodeGen/ARM64/atomic-128.ll
+++ b/llvm/test/CodeGen/ARM64/atomic-128.ll
@@ -86,9 +86,9 @@
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
-; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
+; CHECK: cset [[LOCMP:w[0-9]+]], ls
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
-; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, gt
+; CHECK: cset [[HICMP:w[0-9]+]], le
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@@ -108,9 +108,9 @@
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
-; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
+; CHECK: cset [[LOCMP:w[0-9]+]], hi
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
-; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, le
+; CHECK: cset [[HICMP:w[0-9]+]], gt
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@@ -130,9 +130,9 @@
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
-; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
+; CHECK: cset [[LOCMP:w[0-9]+]], ls
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
-; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, hi
+; CHECK: cset [[HICMP:w[0-9]+]], ls
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@@ -152,9 +152,9 @@
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
-; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
+; CHECK: cset [[LOCMP:w[0-9]+]], hi
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
-; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, ls
+; CHECK: cset [[HICMP:w[0-9]+]], hi
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
diff --git a/llvm/test/CodeGen/ARM64/cast-opt.ll b/llvm/test/CodeGen/ARM64/cast-opt.ll
index 3d7f257..65a871d 100644
--- a/llvm/test/CodeGen/ARM64/cast-opt.ll
+++ b/llvm/test/CodeGen/ARM64/cast-opt.ll
@@ -7,7 +7,7 @@
define zeroext i8 @foo(i32 %i1, i32 %i2) {
; CHECK-LABEL: foo:
-; CHECK: csinc
+; CHECK: cset
; CHECK-NOT: and
entry:
%idxprom = sext i32 %i1 to i64
diff --git a/llvm/test/CodeGen/ARM64/csel.ll b/llvm/test/CodeGen/ARM64/csel.ll
index d0ee61c..975056b 100644
--- a/llvm/test/CodeGen/ARM64/csel.ll
+++ b/llvm/test/CodeGen/ARM64/csel.ll
@@ -2,9 +2,8 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
target triple = "arm64-unknown-unknown"
-; CHECK: foo1
-; CHECK: csinc w{{[0-9]+}}, w[[REG:[0-9]+]],
-; CHECK: w[[REG]], eq
+; CHECK-LABEL: foo1
+; CHECK: cinc w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo1(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%not.tobool = icmp ne i32 %c, 0
@@ -14,9 +13,8 @@
ret i32 %add1
}
-; CHECK: foo2
-; CHECK: csneg w{{[0-9]+}}, w[[REG:[0-9]+]],
-; CHECK: w[[REG]], eq
+; CHECK-LABEL: foo2
+; CHECK: cneg w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo2(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%mul = sub i32 0, %b
@@ -26,9 +24,8 @@
ret i32 %add
}
-; CHECK: foo3
-; CHECK: csinv w{{[0-9]+}}, w[[REG:[0-9]+]],
-; CHECK: w[[REG]], eq
+; CHECK-LABEL: foo3
+; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo3(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%not.tobool = icmp ne i32 %c, 0
@@ -40,8 +37,8 @@
; rdar://11632325
define i32@foo4(i32 %a) nounwind ssp {
-; CHECK: foo4
-; CHECK: csneg
+; CHECK-LABEL: foo4
+; CHECK: cneg
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %a, -1
%neg = sub nsw i32 0, %a
@@ -51,9 +48,9 @@
define i32@foo5(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: foo5
+; CHECK-LABEL: foo5
; CHECK: subs
-; CHECK-NEXT: csneg
+; CHECK-NEXT: cneg
; CHECK-NEXT: ret
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, -1
@@ -64,7 +61,7 @@
; make sure we can handle branch instruction in optimizeCompare.
define i32@foo6(i32 %a, i32 %b) nounwind ssp {
-; CHECK: foo6
+; CHECK-LABEL: foo6
; CHECK: b
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, 0
@@ -116,7 +113,7 @@
; CHECK-LABEL: foo9:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: csinv w0, w[[REG]], w[[REG]], ne
+; CHECK: cinv w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -5
ret i32 %cond
@@ -127,7 +124,7 @@
; CHECK-LABEL: foo10:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: csinv x0, x[[REG]], x[[REG]], ne
+; CHECK: cinv x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -5
ret i64 %cond
@@ -138,7 +135,7 @@
; CHECK-LABEL: foo11:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: csneg w0, w[[REG]], w[[REG]], ne
+; CHECK: cneg w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -4
ret i32 %cond
@@ -149,7 +146,7 @@
; CHECK-LABEL: foo12:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: csneg x0, x[[REG]], x[[REG]], ne
+; CHECK: cneg x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -4
ret i64 %cond
@@ -182,7 +179,7 @@
; CHECK-LABEL: foo15:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: csinc w0, w[[REG]], w[[REG]], le
+; CHECK: cinc w0, w[[REG]], gt
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 2, i32 1
ret i32 %.
@@ -193,7 +190,7 @@
; CHECK-LABEL: foo16:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: csinc w0, w[[REG]], w[[REG]], gt
+; CHECK: cinc w0, w[[REG]], le
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
@@ -204,7 +201,7 @@
; CHECK-LABEL: foo17:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: csinc x0, x[[REG]], x[[REG]], le
+; CHECK: cinc x0, x[[REG]], gt
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 2, i64 1
ret i64 %.
@@ -215,7 +212,7 @@
; CHECK-LABEL: foo18:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: csinc x0, x[[REG]], x[[REG]], gt
+; CHECK: cinc x0, x[[REG]], le
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 1, i64 2
ret i64 %.
diff --git a/llvm/test/CodeGen/ARM64/extract.ll b/llvm/test/CodeGen/ARM64/extract.ll
index 119751c..02e4218 100644
--- a/llvm/test/CodeGen/ARM64/extract.ll
+++ b/llvm/test/CodeGen/ARM64/extract.ll
@@ -6,7 +6,7 @@
%left = shl i64 %in, 19
%right = lshr i64 %in, 45
%val5 = or i64 %left, %right
-; CHECK: extr {{x[0-9]+}}, x0, x0, #45
+; CHECK: ror {{x[0-9]+}}, x0, #45
ret i64 %val5
}
@@ -15,7 +15,7 @@
%left = shl i32 %in, 9
%right = lshr i32 %in, 23
%val5 = or i32 %left, %right
-; CHECK: extr {{w[0-9]+}}, w0, w0, #23
+; CHECK: ror {{w[0-9]+}}, w0, #23
ret i32 %val5
}
diff --git a/llvm/test/CodeGen/ARM64/fast-isel-fcmp.ll b/llvm/test/CodeGen/ARM64/fast-isel-fcmp.ll
index ab86132..f030596 100644
--- a/llvm/test/CodeGen/ARM64/fast-isel-fcmp.ll
+++ b/llvm/test/CodeGen/ARM64/fast-isel-fcmp.ll
@@ -2,144 +2,144 @@
define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
entry:
-; CHECK: @fcmp_float1
+; CHECK-LABEL: @fcmp_float1
; CHECK: fcmp s0, #0.0
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
+; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une float %a, 0.000000e+00
ret i1 %cmp
}
define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp {
entry:
-; CHECK: @fcmp_float2
+; CHECK-LABEL: @fcmp_float2
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
+; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une float %a, %b
ret i1 %cmp
}
define zeroext i1 @fcmp_double1(double %a) nounwind ssp {
entry:
-; CHECK: @fcmp_double1
+; CHECK-LABEL: @fcmp_double1
; CHECK: fcmp d0, #0.0
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
+; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une double %a, 0.000000e+00
ret i1 %cmp
}
define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp {
entry:
-; CHECK: @fcmp_double2
+; CHECK-LABEL: @fcmp_double2
; CHECK: fcmp d0, d1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
+; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une double %a, %b
ret i1 %cmp
}
; Check each fcmp condition
define float @fcmp_oeq(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_oeq
+; CHECK-LABEL: @fcmp_oeq
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
+; CHECK: cset w{{[0-9]+}}, eq
%cmp = fcmp oeq float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ogt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ogt
+; CHECK-LABEL: @fcmp_ogt
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
+; CHECK: cset w{{[0-9]+}}, gt
%cmp = fcmp ogt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_oge(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_oge
+; CHECK-LABEL: @fcmp_oge
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
+; CHECK: cset w{{[0-9]+}}, ge
%cmp = fcmp oge float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_olt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_olt
+; CHECK-LABEL: @fcmp_olt
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
+; CHECK: cset w{{[0-9]+}}, mi
%cmp = fcmp olt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ole(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ole
+; CHECK-LABEL: @fcmp_ole
; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
+; CHECK: cset w{{[0-9]+}}, ls
%cmp = fcmp ole float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ord(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ord
+; CHECK-LABEL: @fcmp_ord
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vs
+; CHECK: cset {{w[0-9]+}}, vc
%cmp = fcmp ord float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_uno(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_uno
+; CHECK-LABEL: @fcmp_uno
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vc
+; CHECK: cset {{w[0-9]+}}, vs
%cmp = fcmp uno float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ugt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ugt
+; CHECK-LABEL: @fcmp_ugt
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ls
+; CHECK: cset {{w[0-9]+}}, hi
%cmp = fcmp ugt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_uge(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_uge
+; CHECK-LABEL: @fcmp_uge
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, mi
+; CHECK: cset {{w[0-9]+}}, pl
%cmp = fcmp uge float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ult(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ult
+; CHECK-LABEL: @fcmp_ult
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ge
+; CHECK: cset {{w[0-9]+}}, lt
%cmp = fcmp ult float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ule(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ule
+; CHECK-LABEL: @fcmp_ule
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, gt
+; CHECK: cset {{w[0-9]+}}, le
%cmp = fcmp ule float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_une(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_une
+; CHECK-LABEL: @fcmp_une
; CHECK: fcmp s0, s1
-; CHECK: csinc {{w[0-9]+}}, wzr, wzr, eq
+; CHECK: cset {{w[0-9]+}}, ne
%cmp = fcmp une float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
diff --git a/llvm/test/CodeGen/ARM64/fast-isel-icmp.ll b/llvm/test/CodeGen/ARM64/fast-isel-icmp.ll
index 68a76c9..971be5c 100644
--- a/llvm/test/CodeGen/ARM64/fast-isel-icmp.ll
+++ b/llvm/test/CodeGen/ARM64/fast-isel-icmp.ll
@@ -4,7 +4,7 @@
entry:
; CHECK: icmp_eq_imm
; CHECK: cmp w0, #31
-; CHECK: csinc w0, wzr, wzr, ne
+; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, 31
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -14,7 +14,7 @@
entry:
; CHECK: icmp_eq_neg_imm
; CHECK: cmn w0, #7
-; CHECK: csinc w0, wzr, wzr, ne
+; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, -7
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -24,7 +24,7 @@
entry:
; CHECK: icmp_eq
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, ne
+; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -34,7 +34,7 @@
entry:
; CHECK: icmp_ne
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, eq
+; CHECK: cset w0, ne
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -44,7 +44,7 @@
entry:
; CHECK: icmp_ugt
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, ls
+; CHECK: cset w0, hi
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -54,7 +54,7 @@
entry:
; CHECK: icmp_uge
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, lo
+; CHECK: cset w0, hs
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -64,7 +64,7 @@
entry:
; CHECK: icmp_ult
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, hs
+; CHECK: cset w0, lo
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -74,7 +74,7 @@
entry:
; CHECK: icmp_ule
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, hi
+; CHECK: cset w0, ls
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -84,7 +84,7 @@
entry:
; CHECK: icmp_sgt
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, le
+; CHECK: cset w0, gt
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -94,7 +94,7 @@
entry:
; CHECK: icmp_sge
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, lt
+; CHECK: cset w0, ge
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -104,7 +104,7 @@
entry:
; CHECK: icmp_slt
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, ge
+; CHECK: cset w0, lt
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -114,7 +114,7 @@
entry:
; CHECK: icmp_sle
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, gt
+; CHECK: cset w0, le
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -124,7 +124,7 @@
entry:
; CHECK: icmp_i64
; CHECK: cmp x0, x1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
+; CHECK: cset w{{[0-9]+}}, le
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -136,7 +136,7 @@
; CHECK: sxth w0, w0
; CHECK: sxth w1, w1
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, ne
+; CHECK: cset w0, eq
%cmp = icmp eq i16 %a, %b
ret i1 %cmp
}
@@ -147,7 +147,7 @@
; CHECK: sxtb w0, w0
; CHECK: sxtb w1, w1
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, ne
+; CHECK: cset w0, eq
%cmp = icmp eq i8 %a, %b
ret i1 %cmp
}
@@ -158,7 +158,7 @@
; CHECK: uxth w0, w0
; CHECK: uxth w1, w1
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, hs
+; CHECK: cset w0, lo
%cmp = icmp ult i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -170,7 +170,7 @@
; CHECK: sxtb w0, w0
; CHECK: sxtb w1, w1
; CHECK: cmp w0, w1
-; CHECK: csinc w0, wzr, wzr, le
+; CHECK: cset w0, gt
%cmp = icmp sgt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -182,7 +182,7 @@
; CHECK: icmp_i16_signed_const
; CHECK: sxth w0, w0
; CHECK: cmn w0, #233
-; CHECK: csinc w0, wzr, wzr, ge
+; CHECK: cset w0, lt
; CHECK: and w0, w0, #0x1
%cmp = icmp slt i16 %a, -233
%conv2 = zext i1 %cmp to i32
@@ -194,7 +194,7 @@
; CHECK: icmp_i8_signed_const
; CHECK: sxtb w0, w0
; CHECK: cmp w0, #124
-; CHECK: csinc w0, wzr, wzr, le
+; CHECK: cset w0, gt
; CHECK: and w0, w0, #0x1
%cmp = icmp sgt i8 %a, 124
%conv2 = zext i1 %cmp to i32
@@ -206,7 +206,7 @@
; CHECK: icmp_i1_unsigned_const
; CHECK: and w0, w0, #0x1
; CHECK: cmp w0, #0
-; CHECK: csinc w0, wzr, wzr, hs
+; CHECK: cset w0, lo
; CHECK: and w0, w0, #0x1
%cmp = icmp ult i1 %a, 0
%conv2 = zext i1 %cmp to i32
diff --git a/llvm/test/CodeGen/ARM64/fcmp-opt.ll b/llvm/test/CodeGen/ARM64/fcmp-opt.ll
index ae7cfec..e79eb9c 100644
--- a/llvm/test/CodeGen/ARM64/fcmp-opt.ll
+++ b/llvm/test/CodeGen/ARM64/fcmp-opt.ll
@@ -5,7 +5,7 @@
entry:
; CHECK-LABEL: @fcmp_float1
; CHECK: fcmp s0, #0.0
-; CHECK: csinc w0, wzr, wzr, eq
+; CHECK: cset w0, ne
%cmp = fcmp une float %a, 0.000000e+00
ret i1 %cmp
}
@@ -14,7 +14,7 @@
entry:
; CHECK-LABEL: @fcmp_float2
; CHECK: fcmp s0, s1
-; CHECK: csinc w0, wzr, wzr, eq
+; CHECK: cset w0, ne
%cmp = fcmp une float %a, %b
ret i1 %cmp
}
@@ -23,7 +23,7 @@
entry:
; CHECK-LABEL: @fcmp_double1
; CHECK: fcmp d0, #0.0
-; CHECK: csinc w0, wzr, wzr, eq
+; CHECK: cset w0, ne
%cmp = fcmp une double %a, 0.000000e+00
ret i1 %cmp
}
@@ -32,7 +32,7 @@
entry:
; CHECK-LABEL: @fcmp_double2
; CHECK: fcmp d0, d1
-; CHECK: csinc w0, wzr, wzr, eq
+; CHECK: cset w0, ne
%cmp = fcmp une double %a, %b
ret i1 %cmp
}
diff --git a/llvm/test/CodeGen/ARM64/fp128.ll b/llvm/test/CodeGen/ARM64/fp128.ll
index a481c79..6aef6f5 100644
--- a/llvm/test/CodeGen/ARM64/fp128.ll
+++ b/llvm/test/CodeGen/ARM64/fp128.ll
@@ -133,7 +133,7 @@
%val = fcmp ole fp128 %lhs, %rhs
; CHECK: bl __letf2
; CHECK: cmp w0, #0
-; CHECK: csinc w0, wzr, wzr, gt
+; CHECK: cset w0, le
ret i1 %val
; CHECK: ret
@@ -150,11 +150,11 @@
%val = fcmp ugt fp128 %lhs, %rhs
; CHECK: bl __gttf2
; CHECK: cmp w0, #0
-; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
+; CHECK: cset [[GT:w[0-9]+]], gt
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
-; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
+; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr w0, [[UNORDERED]], [[GT]]
ret i1 %val
@@ -173,11 +173,11 @@
%cond = fcmp olt fp128 %lhs, %rhs
; CHECK: bl __getf2
; CHECK: cmp w0, #0
-; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
+; CHECK: cset [[OGE:w[0-9]+]], ge
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
-; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
+; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
diff --git a/llvm/test/CodeGen/ARM64/icmp-opt.ll b/llvm/test/CodeGen/ARM64/icmp-opt.ll
index f88399b..7b12ed7 100644
--- a/llvm/test/CodeGen/ARM64/icmp-opt.ll
+++ b/llvm/test/CodeGen/ARM64/icmp-opt.ll
@@ -10,7 +10,7 @@
; CHECK-LABEL: t1:
; CHECK-NOT: movn
; CHECK: cmp x0, #0
-; CHECK: csinc w0, wzr, wzr, lt
+; CHECK: cset w0, ge
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
ret i32 %conv
diff --git a/llvm/test/CodeGen/ARM64/neon-v1i1-setcc.ll b/llvm/test/CodeGen/ARM64/neon-v1i1-setcc.ll
index d7a0771..74e3af8 100644
--- a/llvm/test/CodeGen/ARM64/neon-v1i1-setcc.ll
+++ b/llvm/test/CodeGen/ARM64/neon-v1i1-setcc.ll
@@ -7,7 +7,7 @@
define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
; CHECK-LABEL: test_sext_extr_cmp_0:
; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK: csinc
+; CHECK: cset
%1 = icmp sge <1 x i64> %v1, %v2
%2 = extractelement <1 x i1> %1, i32 0
%vget_lane = sext i1 %2 to i64
diff --git a/llvm/test/CodeGen/ARM64/xaluo.ll b/llvm/test/CodeGen/ARM64/xaluo.ll
index bda41b10..6cffbde 100644
--- a/llvm/test/CodeGen/ARM64/xaluo.ll
+++ b/llvm/test/CodeGen/ARM64/xaluo.ll
@@ -7,7 +7,7 @@
entry:
; CHECK-LABEL: saddo.i32
; CHECK: adds w8, w0, w1
-; CHECK-NEXT: csinc w0, wzr, wzr, vc
+; CHECK-NEXT: cset w0, vs
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -19,7 +19,7 @@
entry:
; CHECK-LABEL: saddo.i64
; CHECK: adds x8, x0, x1
-; CHECK-NEXT: csinc w0, wzr, wzr, vc
+; CHECK-NEXT: cset w0, vs
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -31,7 +31,7 @@
entry:
; CHECK-LABEL: uaddo.i32
; CHECK: adds w8, w0, w1
-; CHECK-NEXT: csinc w0, wzr, wzr, lo
+; CHECK-NEXT: cset w0, hs
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -43,7 +43,7 @@
entry:
; CHECK-LABEL: uaddo.i64
; CHECK: adds x8, x0, x1
-; CHECK-NEXT: csinc w0, wzr, wzr, lo
+; CHECK-NEXT: cset w0, hs
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -55,7 +55,7 @@
entry:
; CHECK-LABEL: ssubo.i32
; CHECK: subs w8, w0, w1
-; CHECK-NEXT: csinc w0, wzr, wzr, vc
+; CHECK-NEXT: cset w0, vs
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -67,7 +67,7 @@
entry:
; CHECK-LABEL: ssubo.i64
; CHECK: subs x8, x0, x1
-; CHECK-NEXT: csinc w0, wzr, wzr, vc
+; CHECK-NEXT: cset w0, vs
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -79,7 +79,7 @@
entry:
; CHECK-LABEL: usubo.i32
; CHECK: subs w8, w0, w1
-; CHECK-NEXT: csinc w0, wzr, wzr, hs
+; CHECK-NEXT: cset w0, lo
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -91,7 +91,7 @@
entry:
; CHECK-LABEL: usubo.i64
; CHECK: subs x8, x0, x1
-; CHECK-NEXT: csinc w0, wzr, wzr, hs
+; CHECK-NEXT: cset w0, lo
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -105,7 +105,7 @@
; CHECK: smull x8, w0, w1
; CHECK-NEXT: lsr x9, x8, #32
; CHECK-NEXT: cmp w9, w8, asr #31
-; CHECK-NEXT: csinc w0, wzr, wzr, eq
+; CHECK-NEXT: cset w0, ne
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -119,7 +119,7 @@
; CHECK: mul x8, x0, x1
; CHECK-NEXT: smulh x9, x0, x1
; CHECK-NEXT: cmp x9, x8, asr #63
-; CHECK-NEXT: csinc w0, wzr, wzr, eq
+; CHECK-NEXT: cset w0, ne
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -132,7 +132,7 @@
; CHECK-LABEL: umulo.i32
; CHECK: umull x8, w0, w1
; CHECK-NEXT: cmp xzr, x8, lsr #32
-; CHECK-NEXT: csinc w0, wzr, wzr, eq
+; CHECK-NEXT: cset w0, ne
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -145,7 +145,7 @@
; CHECK-LABEL: umulo.i64
; CHECK: umulh x8, x0, x1
; CHECK-NEXT: cmp xzr, x8
-; CHECK-NEXT: csinc w8, wzr, wzr, eq
+; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: mul x9, x0, x1
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0